BJT Selector 3D Cross-Point Memory Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Three-terminal selection devices in 3D memory devices face challenges such as large size, complex processing, and incompatibility with 3D multilayer back-end-of-line stacking due to high thermal processing requirements, limiting their integration in cross-point memory structures.
Innovation Solution
The use of bipolar junction transistor (BJT) selector devices with a stacked configuration, employing pulsed laser annealing and low-temperature epitaxial growth, where the base is made of germanium or SiGe and the emitter of silicon, enabling larger transistor gain and flexibility in addressing and error correction, and allowing for 3D multilayer BEOL stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If three-terminal selection devices (transistors) are used in 3D memory devices, then relatively large ON currents and bidirectional operation are achieved, but relatively large size and device complexity increase
Solution Approach 1:
The transistor structure is segmented into distinct doped semiconductor layers (first doped semiconductor layer, second doped semiconductor layer, third doped semiconductor layer) that can be independently formed and controlled. This segmentation allows each layer to be optimized for specific functions while maintaining overall device performance.
Solution Approach 2:
The invention transitions from planar transistor structures to vertically stacked three-dimensional structures. By stacking multiple doped semiconductor layers in the vertical dimension, the device achieves enhanced ON current and bidirectional operation while maintaining a compact footprint that reduces overall device complexity.
2Power
If three-terminal selection devices are used in 3D memory devices, then relatively large ON currents and bidirectional operation are achieved, but relatively large size is incurred
Solution Approach 1:
The transistor structure is transitioned from a planar configuration to a vertically stacked three-dimensional configuration. By utilizing the vertical dimension for stacking multiple doped semiconductor layers, the device achieves enhanced ON current while maintaining a compact lateral footprint, thereby reducing overall device size.
Solution Approach 2:
Multiple functional layers are nested within a compact vertical structure. The first, second, and third doped semiconductor layers are stacked and integrated in a nested configuration, allowing each layer to contribute to the overall ON current while minimizing the lateral space required.
3Adaptability or versatility
If three-terminal selection devices are used in 3D memory devices, then bidirectional operation and tunability are achieved, but incompatibility with 3D multilayer back-end-of-line stacking occurs due to high thermal processing budget
Solution Approach 1:
The invention changes the thermal processing parameters by using low-temperature epitaxial growth and pulsed laser annealing processes. These parameter changes enable the formation of doped semiconductor layers at temperatures compatible with back-end-of-line stacking, while still achieving the desired bidirectional operation and device tunability.
Solution Approach 2:
The invention replaces conventional high-temperature thermal processing with pulsed laser annealing. This substitution uses localized optical energy delivery to achieve the required doping and crystallization without subjecting the entire structure to high thermal budgets, thereby enabling compatibility with 3D multilayer back-end-of-line stacking.
4Manufacturing precision
If conventional high-temperature processing is used for doped semiconductor layers, then proper doping and crystallization are achieved, but incompatibility with 3D multilayer back-end-of-line stacking occurs
Solution Approach 1:
The invention replaces conventional high-temperature thermal processing with pulsed laser annealing. This substitution uses localized optical energy to achieve proper doping activation and crystallization without requiring high thermal budgets, thereby maintaining manufacturing precision while enabling compatibility with 3D multilayer back-end-of-line stacking.
Solution Approach 2:
The invention uses pulsed laser annealing with periodic energy delivery to achieve proper doping and crystallization. The periodic pulsed action allows for controlled energy input that achieves the required manufacturing precision while limiting cumulative thermal exposure, ensuring compatibility with low-temperature back-end-of-line processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient 3D multilayer BEOL stacking of cross-point memory structures with improved transistor performance and flexibility, addressing the size and processing complexity issues of three-terminal devices while maintaining high thermal compatibility.
Implementation Method 1
employing pulsed laser annealing and low-temperature epitaxial growth
Implementation Method 2
employing pulsed laser annealing and low-temperature epitaxial growth
Data Source
AI summary
A method for manufacturing a semiconductor memory device includes forming a first doped semiconductor layer on a conductive layer, forming a second doped semiconductor layer stacked on the first doped semiconductor layer, forming a third doped semiconductor layer stacked on the second doped semiconductor layer, and forming a memory stack layer on the third doped semiconductor layer. The memory stack layer and the first, second and third doped semiconductor layers are patterned into a plurality of pillars spaced apart from each other. In the method, a plurality of extrinsic base layers are formed adjacent the patterned second doped semiconductor layers. The patterned first, second and third doped semiconductor layers in each pillar of the plurality of pillars are components of a bipolar junction transistor device, and the plurality of pillars are parts of a memory cell array having a cross-point structure.