Black Phosphorus FET Thickness Variation for Contact Resistance
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Solution Overview
Problem
Transistors with aggressively miniaturized gate lengths suffer from undesirable short-channel effects and high contact resistance due to the limitations of existing methods using 2D materials like black phosphorus, which impede their performance in radio frequency and digital applications.
Innovation Solution
The method involves forming field-effect transistors with 2D material active regions, specifically black phosphorus, where the thickness of the 2D material is varied between the channel and source/drain regions, and edge passivation or stress layers are applied to reduce contact resistance, and a nonlinear edge profile is created to enhance carrier transport.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate length is reduced to increase packing density and speed performance, then the transistor density and switching speed are improved, but short-channel effects increase causing higher off-state leakage current
Solution Approach 1:
The patent applies different thicknesses of 2D material in different regions: a first thickness in the channel region and a second thickness in the source/drain region. This local variation optimizes carrier transport in the channel while reducing contact resistance at the source/drain interfaces, thereby maintaining low off-state leakage current even with aggressively scaled gate lengths.
2Ease of manufacture
If existing methods are used to fabricate transistors with 2D material channels, then the fabrication process is simplified, but contact resistance increases limiting RF performance
Solution Approach 1:
The patent implements a non-uniform thickness profile where the 2D material has a first thickness in the channel region and a second thickness in the source/drain region. This local differentiation reduces contact resistance at the source/drain contacts while maintaining the structural simplicity of the overall fabrication process.
Solution Approach 2:
The patent introduces thickness variation as an additional degree of freedom in the vertical dimension, creating a three-dimensional thickness profile across the two-dimensional material layer. This dimensional change enables simultaneous optimization of channel performance and contact resistance without complicating the planar fabrication process.
3Device complexity
If uniform thickness 2D material is used throughout the channel and source/drain regions, then the material structure is simplified, but contact resistance increases and carrier mobility decreases
Solution Approach 1:
The patent employs a spatially varying thickness profile where the 2D material thickness is optimized locally: thinner in the channel region for high carrier mobility and thicker in the source/drain region for low contact resistance. This local optimization improves overall device performance without significantly increasing structural complexity.
Data Source
AI summary
Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.