Zero Crossing Detection Filter for Brushless DC Motors
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Solution Overview
Problem
Classical zero cross detection methods in brushless DC motors suffer from false zero crossings due to ringing noise, leading to jitter, torque ripple, and stalling issues, especially at higher speeds, and existing filtering methods introduce significant phase lag or are impractical to implement.
Innovation Solution
A digital majority filter using an n-bit shift register and analog multiplexer to extract true zero crossings, with a predictable group delay, allowing for accurate zero crossing detection and reducing hardware costs by using microcontroller peripherals and lookup tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If digital filtering through a flip flop clocked by PWM signal is used to remove ringing noise, then false zero crossings are reduced, but significant phase lag is introduced causing motor stalling and commutation failure
Solution Approach 1:
The patent segments the filtering process into multiple independent stages: an analog front-end filter for high-frequency ringing rejection, followed by a digital filter processed through SPI/UART peripherals. This segmentation allows each stage to operate at optimal frequencies without introducing excessive phase lag to the overall system.
Solution Approach 2:
The patent introduces intermediary components including an analog multiplexer that selectively routes phase signals, and microcontroller peripherals (SPI/UART) that act as intermediate processing stages. These intermediaries enable signal conditioning and filtering without requiring direct high-speed digital processing that would introduce latency.
2Object-affected harmful factors
If analog filters are used to filter PWM frequency, then ringing noise is reduced, but filtering delay varies with component tolerance, aging, and temperature
Solution Approach 1:
The patent replaces purely analog filtering mechanisms with a hybrid approach that substitutes digital processing for the final filtering stage. The analog front-end handles high-frequency ringing rejection, while digital filters processed through microcontroller peripherals handle the zero-cross detection filtering, eliminating dependence on analog component tolerances and environmental variations.
Solution Approach 2:
The patent changes the operating parameters of the filtering system by using a fixed PWM frequency assumption to design the analog front-end filter, then using digital filtering with predictable group delay characteristics. This allows the system to maintain consistent filtering performance across temperature and aging variations.
3Measurement precision
If PWM frequency is fixed to maintain filtering delay characteristics, then filtering consistency is improved, but thermal management capability is reduced
Solution Approach 1:
The patent segments the filtering architecture into an analog front-end designed for a specific PWM frequency range, combined with a digital filtering stage that can adapt to different PWM frequencies. This allows the system to maintain filtering consistency in the analog stage while providing frequency adaptability through digital processing.
4Adaptability or versatility
If flip flop is clocked at multiples of PWM frequency to allow comparisons on both high and low PWM states, then detection coverage is improved, but host microcontroller timebase complexity increases
Solution Approach 1:
The patent makes the filtering system universal by designing it to work with standard microcontroller PWM frequencies and peripheral configurations. The analog front-end filter and digital filtering through SPI/UART peripherals can handle both high and low PWM states without requiring specialized high-speed timebases, making the solution applicable to a wide range of microcontroller platforms.
Data Source
AI summary
In a multi-phase brushless DC motor, a zero crossing N-bit filter includes a comparator and a phase multiplexer. The phase multiplexer connects each motor phase to each of a positive and a negative input of the comparator, with a switch in each connection to form a switch array. A microprocessor is disposed to operate the switches, and is configured to measure a BEMF for a first phase by opening the switches connecting all other phases to the positive input of the comparator and by opening the switch connecting the first phase being measured to the negative input of said comparator. The comparators output is received by a shift register. The microprocessor is configured to respond to a zero crossing when a majority of bits in the shift register change between high and low.