Bleed Circuit Voltage Profile for Memory Read Disturb
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Solution Overview
Problem
Read disturb in memory cells occurs due to voltage stress during read operations, leading to errors in data retrieval from nearby cells, as the voltage applied to read a memory cell can disturb its state and adjacent cells.
Innovation Solution
A bleed circuit is used in conjunction with a voltage driver to adjust the voltage profile during read operations, reducing the voltage applied to memory cells after current sensing to prevent further stress and interference, thereby minimizing read disturb effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage is applied to read a memory cell, then data can be retrieved from the memory cell, but the voltage stress disturbs the state of the memory cell and nearby memory cells causing read disturb errors
Solution Approach 1:
The patent applies periodic voltage pulses with specific timing characteristics to read the memory cell. The voltage is applied in controlled pulses rather than continuous voltage, allowing the memory cell state to be sensed while limiting the total voltage stress exposure that causes read disturb. The periodic nature of the voltage application enables accurate data retrieval while reducing cumulative disturbance to the memory cell and nearby cells.
Solution Approach 2:
The patent modifies voltage profile parameters including amplitude, duration, and timing to optimize the balance between read accuracy and read disturb reduction. By carefully controlling the voltage magnitude and pulse width, the system achieves sufficient signal strength for accurate sensing while keeping the voltage stress below thresholds that would cause unwanted state changes in memory cells.
2Measurement precision
If higher voltage is applied during read operation, then better signal detection is achieved, but greater voltage stress is applied to memory cells increasing read disturb
Solution Approach 1:
The patent employs dynamic voltage adjustment during the read operation, where the voltage profile is optimized based on the specific read condition and memory cell state. The voltage is dynamically controlled to provide sufficient amplitude for accurate current sensing when needed, while automatically reducing voltage stress when the memory cell state can be determined with lower voltage, thereby adapting to real-time conditions to minimize read disturb.
Solution Approach 2:
The patent applies voltage just sufficient for accurate sensing without excessive over-volting. By using partial action - applying only the minimum necessary voltage to achieve reliable current detection - the system avoids the read disturb that would result from higher voltage applications, thus achieving the optimal balance between sensing accuracy and memory cell preservation.
Data Source
AI summary
An integrated circuit memory device having: a memory cell; a current sensor connected to the memory cell; a voltage driver connected to the memory cell; and a bleed circuit connected to the voltage driver. During an operation to read the memory cell, the voltage driver drives a voltage applied on the memory cell. The bleed circuit is activated to reduce the voltage during a time period in which the current sensor operates to determine whether or not at least a predetermined level of current is presented in the memory cell.