Redistribution Layer Blind-Hole Layout for Fine-Pitch Package Flatness
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Solution Overview
Problem
The manufacturing process of fan-out packages in semiconductor packaging faces issues with poor flatness of subsequent film layers due to large holes and variations in hole filling, affecting the structural reliability of fine pitch bumps.
Innovation Solution
A semiconductor package structure with a redistribution structure layer featuring multiple conductive blind holes connecting connecting pads and soldering pads, along with a design that includes a nickel and gold layer on chip connecting pads, enhances structural flatness and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large holes are used to connect connecting pads and soldering pads, then electrical connection is achieved, but the flatness of subsequent film layers deteriorates
Solution Approach 1:
The patent divides a single large conductive hole into multiple smaller conductive blind holes (first, second, and third conductive blind holes) to connect the connecting pad and soldering pad. This segmentation reduces the impact on film layer flatness while maintaining electrical connection reliability, as each smaller hole creates less disturbance to the surrounding dielectric layer and subsequent film deposition.
Solution Approach 2:
The patent applies different designs to different regions: the conductive blind holes are strategically positioned and sized to minimize local disturbance to the dielectric layer, while the connecting pads and soldering pads maintain their required electrical properties. The nickel and gold layers are selectively applied to specific connecting pads to enhance local bonding quality without affecting the overall structure.
2Ease of manufacture
If variations in hole filling process are used, then manufacturing complexity is reduced, but structural reliability of fine pitch bumps deteriorates
Solution Approach 1:
The patent specifies precise parameters for the conductive blind holes including their dimensions (e.g., diameter or width ranges), spacing, and depth to ensure consistent electrical connection without causing flatness issues. The nickel layer thickness (50-200 nm) and gold layer thickness (10-50 nm) are carefully controlled to optimize bonding reliability while maintaining manufacturing feasibility.
Solution Approach 2:
The patent incorporates a nickel layer and gold layer on the connecting pads before forming the fine pitch bumps. This preliminary action prepares the surface with optimal bonding properties, ensuring reliable structural connection for subsequent fine pitch bump formation while allowing the hole filling process to proceed with standard variations.
3Reliability
If conductive blind holes are formed to connect pads, then electrical connection is achieved, but flatness of subsequent film layers deteriorates
Solution Approach 1:
The patent divides the conductive path into multiple separate blind holes rather than using a single large via. This segmentation approach allows each hole to be smaller and more uniformly formed, reducing the overall impact on dielectric layer integrity and subsequent film flatness while achieving the required electrical connection between connecting pads and soldering pads.
Solution Approach 2:
The patent introduces a dielectric layer with embedded conductive blind holes as an intermediary structure between the connecting pads and soldering pads. This intermediary approach allows electrical connection to be achieved through controlled via structures that minimize disturbance to the surrounding film layers, maintaining better flatness compared to direct large-hole connections.
4Reliability
If nickel and gold layers are added to chip connecting pads, then bonding reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies the nickel and gold layers selectively only to the connecting pads that require enhanced bonding properties, rather than coating the entire device structure. This localized application improves bonding reliability at critical interfaces while minimizing the overall complexity and material cost of the device structure.
Solution Approach 2:
The patent uses a composite layer structure of nickel and gold on the connecting pads. The nickel layer provides barrier and bonding properties, while the gold layer provides corrosion resistance and conductivity. This composite material approach achieves superior bonding reliability through material properties rather than increasing structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves structural flatness and reliability by reducing unevenness in subsequent film layers, enhancing the yield of fine pitch bumps and flip chip bonding processes.
Implementation Method 1
the nickel layer covers the top surface and the surrounding surface of the chip connecting pad. The gold layer covers the nickel layer on the top surface of the chip connecting pad.
Data Source
AI summary
A semiconductor package structure includes a redistribution structure layer, at least one chip, an encapsulant, and multiple solder balls. The redistribution structure layer includes multiple first connectors located on a first side. Each first connector includes a connecting pad, a soldering pad, and multiple conductive blind holes located between the connecting pad and the soldering pad. The conductive blind holes are disposed separately from each other and connect the connecting pad and the soldering pad. The chip is disposed on a second side of the redistribution structure layer and electrically connected to the redistribution structure layer. The encapsulant is disposed on the second side and at least covers the chip and the second side. The solder balls are disposed on the first side of the redistribution structure layer and electrically connected to the redistribution structure layer. The solder balls are respectively connected to the connecting pad of each first connector.