3D Package Interconnects via Blind Hole Solder Insertion
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Solution Overview
Problem
The existing three-dimensional packages face difficulties in alignment and stability during joining due to the hemispherical shape of solders formed by capillary phenomenon, leading to unstable connections and increased overall height.
Innovation Solution
A method involving the formation of blind holes, isolation layers, and conductive layers on semiconductor bodies, with the lower end of the conductive layer exposed to facilitate solder insertion during reflow, enhancing joint stability and reducing package height by aligning and inserting the conductive layer and solder into the blind holes of stacked semiconductor bodies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If solder is formed by capillary phenomenon in blind holes, then solder fills the holes automatically, but the solder forms hemispherical shape at the ends making alignment difficult and joining unstable
Solution Approach 1:
The patent applies preliminary action by pre-forming the conductive layer with a flat lower surface and exposing it below the semiconductor body surface before soldering. This preliminary preparation ensures that when solder is applied, it forms a stable planar interface rather than a hemispherical shape, enabling precise alignment and stable joining between stacked semiconductor units.
2Reliability
If solder forms hemispherical shape, then solder fills blind holes completely, but the excess hemispherical solder increases the overall package height
Solution Approach 1:
The patent applies parameter changes by modifying the surface geometry parameter of the conductive layer from hemispherical to flat. By controlling the conductive layer formation process and exposing a planar surface below the semiconductor body, the solder interface changes from a curved hemispherical shape to a flat plane, reducing overall package height while maintaining joint stability through improved alignment.
3Manufacturing precision
If conductive layer lower end is exposed below semiconductor body surface, then solder insertion and alignment are improved, but additional processing steps are required
Solution Approach 1:
The patent merges multiple functions into the conductive layer structure. The conductive layer simultaneously serves as the electrical connection path, the alignment reference surface (with its exposed flat lower end), and the solder mounting substrate. This integration reduces the need for separate alignment features and simplifies the overall manufacturing process despite the additional exposure step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves the alignment and stability of the joint between semiconductor units, reducing the overall height of the three-dimensional package by ensuring a secure connection through the insertion of the conductive layer and solder into blind holes during the reflow process.
Implementation Method 1
the solder enter the first hole 12 and the second hole 22 according to the capillary phenomenon so as to form the first solder 14 and the second solder 24
Data Source
AI summary
The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.