Blind Via Testing via Peripheral Conductive Pattern Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor package manufacturing process faces challenges in efficiently testing and ensuring the electrical connectivity of blind vias on printed circuit boards, particularly due to the complexity of simultaneously testing multiple unit substrate regions, which can lead to unreliable results and decreased productivity.
Innovation Solution
A method involving a strip substrate with unit substrate regions, a peripheral conductive pattern layer, and a connection pattern layer that electrically connects blind vias to the peripheral conductive pattern layer, allowing for sequential electric current testing of each unit substrate region to confirm the integrity of the electrical path through the blind vias, ensuring accurate and reliable connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous testing of multiple unit substrate regions is performed, then productivity is improved, but measurement precision deteriorates due to unreliable test results from conductive paths not passing through blind vias
Solution Approach 1:
The patent divides the strip substrate into multiple unit substrate regions, each with its own peripheral conductive pattern layer. By segmenting the testing process into sequential individual region tests rather than simultaneous multi-region testing, the patent ensures that each test measures only the conductive path through the blind via of that specific region, eliminating interference from other regions and ensuring measurement precision while maintaining productivity through systematic sequential testing
Solution Approach 2:
The peripheral conductive pattern layer serves as an intermediary element that is uniquely connected to the blind via in each unit substrate region. This intermediary structure allows for isolated testing of each region's blind via connectivity by providing a dedicated test path that does not share conductive paths with other regions, thus ensuring reliable measurement results
2Reliability
If complex testing procedures are used to ensure blind via connectivity, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent incorporates the peripheral conductive pattern layer into the manufacturing process before final assembly, establishing dedicated test access points for each unit substrate region's blind via. This preliminary action embeds the testing capability directly into the structure, allowing for simple sequential electrical continuity tests rather than complex post-assembly testing procedures
Solution Approach 2:
The structure itself provides the testing mechanism through the peripheral conductive pattern layer that is inherently connected to each blind via. The design makes the structure self-testable by providing built-in test paths that require only simple electrical continuity measurement, eliminating the need for external complex testing equipment or procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of electric current tests by ensuring each unit substrate region is tested individually, reducing the risk of false positives from conductive paths not passing through the blind vias and improving the overall manufacturing process by confirming the integrity of the electrical connections.
Implementation Method 1
a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer
Implementation Method 2
A test for confirming a current flowing through each of the blind vias is performed by applying a power supply voltage between circuit wires connected to the blind vias
Data Source
AI summary
A method of manufacturing a semiconductor package is provided. The method includes providing a strip substrate having a plurality of unit substrate regions that are spaced apart from each other by a periphery region and have blind vias, a peripheral conductive pattern layer disposed in the periphery region, and a connection pattern layer electrically connecting the blind vias to the peripheral conductive pattern layer. Semiconductor chips are disposed on the plurality of unit substrate regions, respectively. Conductive wires are formed to electrically connect connection pads disposed on the plurality of unit substrate regions to bonding pads disposed on the semiconductor chips. The connection pads are electrically connected to the blind vias, and forming the conductive wires includes performing a test for confirming a current that flows between each conductive wire and the peripheral conductive pattern layer through the unit substrate region.