Block Aligner Deskew for PCIe Gen3 Lane Timing
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Solution Overview
Problem
The PCIe Gen3 protocol introduces indeterminism due to varying dead-cycle behavior across different lanes of a multiple lane interface, causing latency and signal integrity issues, which existing deskew buffer solutions are costly and vulnerable to corner cases.
Innovation Solution
A block aligner with additional delay elements and a 2-bit timer forces simultaneous dead cycles across all lanes, using a duplicate set of input data banks and a multiplexer to align timing, and a 2-bit counter to synchronize dead cycles, eliminating indeterminism and reducing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dead cycles are inserted to correct underflow conditions in each lane, then data integrity is maintained, but latency increases and indeterminism is introduced across lanes
Solution Approach 1:
The patent merges the dead cycle insertion logic across all lanes by using a shared counter and control mechanism. Instead of allowing each lane to independently insert dead cycles at different times, the system combines the control logic to synchronize dead cycle insertion across lanes, thereby maintaining data integrity while reducing the indeterminism and latency variability caused by unsynchronized dead cycles
2Stability of the object's composition
If traditional deskew buffers are used to align lanes, then timing alignment is achieved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the essential function of timing alignment from complex deskew buffers and implements it through a simplified mechanism using delay elements and a counter-based control system. By taking out only the necessary timing adjustment functionality and implementing it through simple logic circuits rather than large buffers, the system achieves timing alignment while significantly reducing device complexity and cost
Solution Approach 2:
The patent replaces expensive, complex deskew buffers with inexpensive logic circuits consisting of delay elements, multiplexers, and counters. These simple components achieve the same timing alignment function at a fraction of the cost and complexity, effectively using cheap alternatives to replace expensive traditional solutions
3Ease of operation
If sync headers are removed every 16 cycles to facilitate processing, then link layer processing is simplified, but underflow conditions occur requiring dead cycle insertion
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-synchronizing the dead cycle insertion points across all lanes using a shared counter. Instead of reacting to underflow conditions as they occur in each lane independently, the system preliminarily determines the timing of dead cycle insertion for all lanes simultaneously, simplifying the overall management of dead cycles while maintaining processing simplicity
Data Source
AI summary
A method and apparatus to deskew dead cycles is described using a block aligner. In one example a method includes receiving a sequence of bytes into a first buffer from each lane of a multiple lane peripheral device bus and receiving the sequence of bytes into a second buffer delayed one clock cycle from the first buffer. The method further includes providing the sequence of bytes from the first buffer to an output buffer, counting clock cycles of data as the data is received into the first and second buffers, upon reaching a predetermined count, inserting a dead cycle into the output buffer, and after inserting the dead cycle providing the sequence of bytes from the second buffer instead of the first buffer to the output buffer.