Block Closure Techniques for 3D MLC Flash Memory
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Solution Overview
Problem
Flash memory devices face reliability issues due to threshold voltage shifting over time, leading to data instability and increased latency in accessing stored data, as charge leakage causes voltage drift, affecting data storage density and accessibility.
Innovation Solution
Implementing a block closure technique that maintains a common set of cell voltage distribution (CVD) tracking parameters and error correcting code (ECC) control data for closed multi-level cell (MLC) blocks, allowing data access without re-adjusting read circuitry or ECC decoders, thereby reducing latency and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple sets of CVD tracking parameters and ECC control data are maintained for different word lines in closed MLC blocks, then data reliability can be maintained, but device complexity and operational overhead increase
Solution Approach 1:
The patent merges multiple sets of CVD tracking parameters and ECC control data into a single common set that is shared across all word lines in a closed MLC block. This consolidation reduces the complexity of parameter management while maintaining data reliability, as the common parameters are applied uniformly to all word lines in the closed block.
Solution Approach 2:
The common set of CVD tracking parameters and ECC control data serves multiple word lines simultaneously, making the parameter management system universal. Instead of maintaining separate parameters for each word line, the same parameter set is used across all word lines in the closed block, reducing overhead while preserving reliability.
2Measurement precision
If read circuitry and ECC decoder are re-adjusted for each word line in closed MLC blocks, then data accuracy can be maintained, but access latency increases
Solution Approach 1:
The patent performs preliminary action by pre-establishing a common set of CVD tracking parameters and ECC control data that can be immediately applied to all word lines in a closed MLC block. This eliminates the need for real-time re-adjustment of read circuitry and ECC decoder for each word line, thereby reducing access latency while maintaining data accuracy through the pre-configured common parameters.
3Ease of manufacture
If conventional block closure is implemented without common parameter maintenance, then implementation simplicity is maintained, but read operation latency increases
Solution Approach 1:
The patent ensures continuity of useful action by maintaining the common set of CVD tracking parameters and ECC control data throughout the operation of closed MLC blocks. This continuous availability of common parameters eliminates interruptions and re-adjustments during read operations, reducing latency while keeping the implementation relatively simple through the use of a single shared parameter set.
Data Source
AI summary
A data storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.