Soft Input-Output Block Code Mapping for LLR Decoding
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Solution Overview
Problem
Current coding techniques lack efficient methods for generating soft information using other soft information, particularly in hardware implementations like FPGAs or ASICs, which are capable of performing complex computations but struggle with generating log-likelihood ratios (LLRs) for block codes effectively.
Innovation Solution
The development of a technique that uses a soft input, soft output mapper and demapper to generate LLRs for block codes by iteratively performing max* functions and maximum functions, allowing for the transformation of LLRs from message bits to codeword bits and vice versa, enabling the use of these techniques in hardware such as FPGAs or ASICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If hard decision decoding is used, then device complexity is reduced, but information loss increases due to lack of probability information
Solution Approach 1:
The patent transforms hard decisions into soft information by computing log-likelihood ratios (LLRs) that represent the probability that a decoded bit is correct. This parameter transformation allows the system to retain probability information while maintaining compatibility with standard decoding operations. The LLR values are computed based on the distance between the received signal and possible transmitted signals, providing a measure of confidence for each bit decision.
Solution Approach 2:
The patent introduces an intermediary soft information generation stage between the channel decoder and the block code decoder. This intermediary computes LLRs for the block code bits based on the channel decoder output and the codebook structure, providing probabilistic information to the block code decoder without requiring it to be aware of the channel coding details. This mediator enables soft decision decoding while maintaining modular system design.
2Measurement precision
If soft information processing is implemented, then decoding accuracy improves, but device complexity increases due to computational requirements
Solution Approach 1:
The patent segments the soft information generation process into distinct stages: (1) channel decoder produces hard or soft decisions, (2) LLR computation for block code bits based on codebook matching, (3) iterative refinement using computed LLRs. This segmentation allows the system to perform soft decision processing in manageable steps, reducing the computational burden compared to exhaustive soft decision decoding while maintaining accuracy benefits.
Solution Approach 2:
The patent implements partial soft decision processing by computing LLRs only for the block code bits that need refinement, rather than performing full soft decision decoding for all bits. The system computes LLRs iteratively, refining only the necessary portions of the decoded message. This partial action approach achieves significant accuracy improvement with reduced computational complexity compared to complete soft decision processing.
3Reliability
If iterative max* functions are used to generate LLRs, then soft information quality improves, but processing time increases
Solution Approach 1:
The patent uses periodic iterative refinement where LLRs are computed in multiple passes, with each pass improving the quality of soft information. The iterative process periodically updates LLR values based on the current decoding state and codebook structure, converging to high-quality soft information. This periodic action allows the system to balance processing time and reliability by stopping iterations when sufficient accuracy is achieved or when a predetermined number of iterations is reached.
Data Source
AI summary
A log-likelihood ratio (LLR) for a bit bi in a message is determined by generating a first term, including by summing LLRs corresponding to bits in a first codeword having a specified value. The first codeword has a corresponding first message and bit bi of the first message corresponds to a 0. A second term is generated, including by summing LLRs corresponding to bits in a second codeword having the specified value. The second codeword has a corresponding second message and bit bi of the second message corresponds to a 1. The LLR for bit bi in the message is generated based at least in part on the first term and the second term.