Block Copolymer Self-Assembly for Memory Device Wiring
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge lies in scaling down memory cell size while reducing the number of high-cost steps such as lithography and etching, which are technically difficult and costly in current memory device manufacturing processes.
Innovation Solution
The method involves using a block copolymer as a self-assembling material to form metal wiring in a memory cell array, allowing for phase separation and pattern formation without high-precision lithography, thereby reducing the number of complex and costly steps in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If lithography and etching steps are used for scaling down memory cell size, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The block copolymer layer performs self-assembly to automatically form the desired pattern structure without requiring external lithography guidance. The system serves itself by utilizing the inherent phase separation behavior of the block copolymer to create the wiring pattern, eliminating the need for complex lithography and etching processes while achieving precise scaling down of memory cell size
Solution Approach 2:
The invention changes the physical and chemical parameters of the polymer layer by using a block copolymer with specific composition ratios and performing thermal treatment at controlled temperatures. These parameter changes induce phase separation that naturally forms the desired pattern, replacing the need for high-precision lithography while maintaining manufacturing precision
2Manufacturing precision
If lithography and etching steps are used for pattern formation, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The block copolymer layer performs self-assembly to automatically form the desired pattern structure without requiring external lithography guidance. The system serves itself by utilizing the inherent phase separation behavior of the block copolymer to create the wiring pattern, eliminating the need for complex lithography and etching processes while achieving precise scaling down of memory cell size
Solution Approach 2:
The invention uses a relatively simple and inexpensive block copolymer material that can be deposited as a thin film and then discarded after serving its patterning function. This disposable approach to pattern formation avoids the need for expensive lithography equipment and complex etching processes, significantly reducing manufacturing cost while maintaining pattern formation precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and enables the scaling down of memory devices by forming metal wiring and memory layers in a cross-point type organic molecular memory device, achieving low-cost production.
Implementation Method 1
performing thermal treatment on the block copolymer layer, the thermal treatment separating the block copolymer layer such that a first phase containing the first polymer and extending in the first direction and a second phase containing the second polymer and extending in the first direction are alternately arrayed
Data Source
AI summary
A method for manufacturing a memory device of an embodiment includes: forming on a substrate a block copolymer layer which contains a first polymer and a second polymer having lower surface energy than that of the first polymer; performing thermal treatment on the block copolymer layer, to separate the block copolymer layer such that a first phase containing the first polymer and extending in the first direction and a second phase containing the second polymer and extending in the first direction are alternately arrayed; selectively forming on the first phase a first metal wiring layer extending in the first direction; forming on the first metal wiring layer a memory layer where resistance changes by application of a voltage; and forming on the memory layer a second metal wiring layer which extends in a second direction intersecting in the first direction.