Block-Based Data Compression for Off-Chip Memory Bandwidth

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Solution Overview

Problem

Hardware accelerators and convolutional neural networks (CNNs) on processor chips face memory capacity limitations, leading to bandwidth bottlenecks when transferring data from off-chip memory due to incompatible compression techniques with their operating frequencies.

Innovation Solution

An off-chip data compression technique that splits data into blocks and applies lossless compression methods like run-length encoding (RLE) or partial Huffman encoding based on block characteristics, generating headers for decoding, and enabling parallel processing to optimize bandwidth and reduce memory requirements.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If data is compressed using traditional lossless compression techniques, then data size is reduced, but compatibility with hardware accelerator operating frequencies is lost

Engineering Contradiction:
Improvedata sizeVSAvoidcompatibility with hardware accelerator frequencies
Core Design Contradiction:
Quantity of substanceVSAdaptability or versatility

Solution Approach 1:

The patent divides data into fixed-size blocks that can be independently compressed and processed. Each block is handled separately through the memory interface, allowing parallel processing that matches the hardware accelerator's operating frequency requirements while achieving overall data compression through selective application of compression algorithms to individual blocks.

Inventive Principle:
Principle #1Segmentation

2Speed

If data is transferred from off-chip memory without compression, then processing speed is maintained, but bandwidth bottlenecks occur

Engineering Contradiction:
Improveprocessing speedVSAvoidbandwidth
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent applies compression algorithms to data blocks before they are transferred from off-chip memory through the memory interface to the hardware accelerator. This preliminary compression reduces the total volume of data that needs to be transferred, eliminating bandwidth bottlenecks while the hardware accelerator processes the compressed data at its native operating frequency without speed degradation.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If compression algorithms are applied to all data blocks, then data size is reduced, but processing complexity increases

Engineering Contradiction:
Improvedata sizeVSAvoidprocessing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent evaluates each data block individually and applies compression algorithms selectively based on the specific characteristics of that block. Some blocks may be compressed while others are left uncompressed, optimizing the balance between data size reduction and processing complexity by adapting the compression approach to local data properties rather than applying a uniform compression strategy to all data.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11075647B2Methods and apparatus to compress data
Publication Date: 2021.07.27 MOVIDIUS LTD
  • US11075647B2 patent drawing
  • US11075647B2 patent drawing
  • US11075647B2 patent drawing

AI summary

Methods, apparatus, systems and articles of manufacture to compress data are disclosed. An example apparatus includes an off-chip memory to store data; a data slicer to split a dataset into a plurality of blocks of data; a data processor to select a first compression technique for a first block of the plurality of blocks of data based on first characteristics of the first block; and select a second compression technique for a second block of the plurality of blocks of data based on second characteristics of the second block; a first compressor to compress the first block using the first compression technique to generate a first compressed block of data; a second compressor to compress the second block using the second compression technique to generate a second compressed block of data; a header generator to generate a first header identifying the first compression technique and a second header identifying the second compression technique; and an interface to transmit the first compressed block of data with the first header and the second compressed block of data with the second header to be stored in the off chip memory.