Block Code Decoder Using Erasure Identification for Bursty Errors

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Solution Overview

Problem

Existing block code decoders face limitations in increasing error detection and correction capabilities, particularly in handling bursty errors, as current methods like configuring inner decoders for soft bit estimates are difficult to implement effectively.

Innovation Solution

An erasures assisted block code decoder is introduced, comprising a first block decoder, an erasures processor, and a second block decoder, which identifies and utilizes erasures in un-decodable blocks to improve decoding capabilities by converting errors into erasures, thereby increasing the number of correctable errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If code concatenation with outer block code and inner convolutional code is applied, then error detection and correction capability is increased, but device complexity increases

Engineering Contradiction:
Improveerror detection and correction capabilityVSAvoiddecoder structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The decoder is divided into multiple functional components: a first block decoder for initial decoding, an erasure processor for identifying erroneous positions, and a second block decoder for final decoding. This segmentation allows each component to perform a specific function, simplifying the overall complex task of handling bursty errors while maintaining high error correction capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The erasure processor acts as an intermediary component between the first and second block decoders. It processes the output from the first decoder, identifies erasure positions using parity check equations, and provides this erasure information to the second decoder. This intermediary function enables the system to handle bursty errors effectively without requiring a completely complex redesign of the entire decoder.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If inner decoder is configured for soft bit estimates, then error correction capability is improved, but ease of manufacture decreases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidimplementation difficulty
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention uses hard decision outputs from the first block decoder as disposable intermediate results. Even though these hard decisions may contain errors, they are processed through the erasure processor to identify erasure positions. This approach avoids the complexity of implementing soft decision decoding while still achieving improved error correction capability through the erasure identification mechanism.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The system changes the parameter representation from soft bit estimates to hard decision outputs with associated erasure flags. By transforming the output format of the first decoder into erasure position information, the system achieves error correction capability improvement without the manufacturing complexity of soft decision decoding. The erasure processor transforms hard decisions into useful erasure information that the second decoder can utilize.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the number of parity bits is increased, then error detection and correction capability is improved, but loss of information increases

Engineering Contradiction:
Improveerror detection and correction capabilityVSAvoiddata rate reduction
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The erasure processor performs preliminary identification of erasure positions before the second block decoder processes the data. By using the parity check equations to identify which positions are likely erroneous, the system can focus the error correction capability on specific positions rather than requiring increased redundancy across all data. This preliminary action allows efficient use of the existing parity bits.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system changes the approach from increasing the number of parity bits to changing how existing parity bits are utilized. Instead of adding more redundancy, the erasure processor reuses the existing parity check equations to identify erasure positions, thereby improving error correction capability without increasing the parity overhead and maintaining the original data rate.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8065593B2Erasures assisted block code decoder and related method
Publication Date: 2011.11.22 ENTROPIC COMM INC
  • US8065593B2 patent drawing
  • US8065593B2 patent drawing
  • US8065593B2 patent drawing

AI summary

An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.