Block Decoder Level Shifter Layout With Shared Wells
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Solution Overview
Problem
Conventional flash memory designs require a large layout area due to the increasing number of blocks and block decoders, necessitating a reduction in total circuit layout area while maintaining system reliability.
Innovation Solution
A block decoder and level shifter design incorporating four transistors (M1, M2, M3, M4) with specific voltage coupling and control node configurations, where M1 and M2 are enhancement-type transistors and M4 is a P-type transistor, forming a positive feedback loop to reduce layout area and enhance grounding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of blocks and block decoders is increased to meet higher circuit density requirements, then the memory capacity and functionality are improved, but the total layout area becomes excessively large
Solution Approach 1:
The patent merges the level shifter and block decoder into a single integrated structure where the level shifter is positioned between the block decoder and bit line. This integration allows shared semiconductor wells between the level shifter transistors and block decoder transistors, reducing the total layout area while maintaining the required number of blocks for high-density memory
2Reliability
If conventional depletion-type transistors are used in the level shifter, then the circuit functionality is maintained, but the system reliability is insufficient
Solution Approach 1:
The patent changes the transistor type parameter from depletion-type to enhancement-type for the level shifter transistors. This parameter change improves system reliability by providing better grounding and more stable operation, while the integrated design maintains manageable complexity through shared semiconductor wells
Data Source
AI summary
A block decoder of nonvolatile memory includes a level shifter and a decoder. A first transistor has a control terminal coupled to a first control node, a first terminal coupled to an output node, and a second terminal coupled to a first supply voltage. A second transistor has a control terminal coupled to a second control node, a first terminal coupled to a ground voltage, and a second terminal coupled to the output node. A third transistor has a control terminal coupled to the output node, a first terminal coupled to a first node, and a second terminal coupled to second supply voltage. A fourth transistor has a control terminal coupled to the second control node, a first terminal coupled to the first node, and a second terminal coupled to the output node.