Block Decoder Area Reduction via Address Signal Merging

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The increasing demand for high-capacity semiconductor memory devices with reduced refresh requirements necessitates a more integrated design, where the existing block decoder in flash memory devices requires a significant area due to the number of metal lines needed for operation.

Innovation Solution

The use of address mixing signals and enable period signals to control the block decoder, reducing the number of metal lines required by generating control signals and block selection signals, thereby minimizing the area occupied by the block decoder circuit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional block decoder design with separate metal lines for each address signal is used, then the block decoder can operate reliably, but the area occupied by the block decoder increases significantly

Engineering Contradiction:

Improveblock decoder operation reliabilityVSAvoidblock decoder area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges multiple address signals (XA, XB, XC, XD) into two mixed address signals (XAXC and XBXD) by combining adjacent metal lines. This merging reduces the number of separate metal lines from four to two, thereby reducing the block decoder area while maintaining operational reliability through the mixed signal logic that still uniquely identifies each memory block.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The mixed address signals (XAXC and XBXD) serve multiple functions: they simultaneously encode information from four original address lines (XA, XB, XC, XD) and enable the block decoder to distinguish between different memory blocks. This multi-functionality allows the reduced signal set to maintain the same decoding capability as the original four-line system.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Measurement precision

If more metal lines are arranged beside the block decoder to receive address signals, then the block decoder can select memory blocks accurately, but the overall semiconductor memory device area increases

Engineering Contradiction:

Improvememory block selection precisionVSAvoidsemiconductor memory device area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent combines four separate address signal lines (XA, XB, XC, XD) into two mixed signal lines (XAXC, XBXD) by logically merging the address information. This reduces the metal line count from four to two, decreasing the horizontal space required beside the block decoder while preserving the ability to accurately select any of the 4096 memory blocks through the mixed signal encoding.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS8325558B2Block decoder of semiconductor memory device

Publication Date: 2012.12.04 MIMIRIP LLC

AI summary

A block decoder of a semiconductor memory device includes a control signal generation circuit configured to output a control signal in response to a first address mixing signal, a second address mixing signal, and an enable period signal and a block selection signal generation circuit configured to generate a block selection signal for selecting a memory block in response to the control signal.