Block-Based Display Gate Driving for Uniform Signal Timing
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Solution Overview
Problem
Display devices experience gate line delay and signal variation near the end of the gate line, leading to deteriorated display quality due to differences in gate line lengths and varying slew rates across the display panel.
Innovation Solution
The display device is divided into blocks with different gate drivers providing signals through buffers and slew rate controllers to equalize slew rates across sub-gate lines, using dummy gate lines and adjusting inverter counts to maintain consistent signal timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single gate driver provides gate signals to all pixels through a single gate line, then the device structure is simple, but gate line delay increases and display quality deteriorates
Solution Approach 1:
The display panel is divided into multiple blocks (first block, second block, etc.) with each block receiving gate signals through separate sub-gate lines from the gate driver. This segmentation reduces the gate line delay by distributing the signal transmission paths, ensuring that pixels at different distances from the gate driver receive synchronized gate signals, thereby maintaining display quality.
2Area of stationary object
If gate lines are extended to reach distant pixels, then coverage is improved, but gate line delay increases due to longer signal transmission paths
Solution Approach 1:
The gate line is segmented into multiple sub-gate lines, each serving a specific block of pixels. This allows the gate driver to provide signals to distant pixels through multiple shorter paths rather than one long path, reducing overall gate line delay while maintaining full panel coverage.
Solution Approach 2:
Buffers are introduced as intermediary components between the gate driver and the sub-gate lines. These buffers compensate for signal degradation and timing variations over long transmission paths, ensuring that gate signals reach distant pixels with appropriate timing and strength, thereby reducing effective gate line delay.
3Device complexity
If slew rate varies across different gate lines, then signal transmission is simplified, but display quality deteriorates due to inconsistent timing
Solution Approach 1:
The slew rate controller dynamically adjusts the slew rate parameter of gate signals based on the specific sub-gate line and pixel block being served. By changing the slew rate parameter according to transmission distance and conditions, the system achieves consistent signal timing across all gate lines while maintaining manageable control complexity.
Data Source
AI summary
A display device includes a display panel including a first block and a second block, the display panel having a plurality of pixels located therein, and a first gate driver configured to provide a gate signal to the first block and the second block, wherein the first gate driver provides the gate signal to a first sub-gate line connected to the first block through a first buffer and a first slew rate controller, and provides the gate signal to a second sub-gate line connected to the second block through a second buffer, and wherein the first block is closer to the first gate driver than the second block.