Memory Block Family Closure for Temporal Voltage Shift Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory sub-systems fail to adequately address the temporal voltage shift caused by slow charge loss in memory cells, leading to increased bit error rates due to inefficient strategies.
Innovation Solution
Implementing a memory sub-system that tracks temporal voltage shift for grouped block families, applying appropriate voltage offsets based on block affiliation, and performing soft and hard closures to manage the shift, thereby improving bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory sub-systems use traditional closure strategies for block families, then device complexity is reduced, but bit error rates increase due to inadequate addressing of temporal voltage shift
Solution Approach 1:
The patent segments the memory block management into two distinct closure types: soft closure and hard closure. Soft closure is triggered by time-based criteria while hard closure is triggered by temperature-based criteria. This segmentation allows the system to address temporal voltage shift through multiple specialized mechanisms rather than a single complex strategy, thereby improving reliability without overwhelming device complexity.
Solution Approach 2:
The patent implements preliminary tracking of temporal voltage shift characteristics for grouped block families before closure decisions are made. By maintaining metadata that records voltage shift patterns over time and temperature, the system prepares closure criteria in advance, enabling more accurate closure timing that prevents bit errors without requiring complex real-time calculations during operation.
2Reliability
If memory sub-systems implement tracking of temporal voltage shift for all blocks, then bit error rates decrease, but processing and storage resources are consumed
Solution Approach 1:
The patent merges multiple blocks into block families that share common temporal voltage shift characteristics. By grouping blocks with similar access patterns and environmental conditions, the system performs calibration operations on a family basis rather than individually for each block. This merging reduces processing resources while maintaining accurate voltage shift tracking, as demonstrated by the shared metadata structure that serves multiple blocks within a family.
Solution Approach 2:
The patent changes the granularity of tracking from individual blocks to block families, and dynamically adjusts calibration parameters based on temperature and time. By modifying the tracking parameter scope and using temperature-compensated voltage offsets, the system reduces the computational burden while preserving the ability to correct temporal voltage shift effects, thereby lowering energy consumption without sacrificing reliability.
3Measurement precision
If memory sub-systems perform frequent calibration operations, then voltage shift accuracy improves, but productivity decreases due to resource consumption
Solution Approach 1:
The patent implements periodic calibration operations triggered by soft closure events rather than continuous calibration. The calibration is performed at regular intervals defined by the soft closure time criteria, which balances voltage shift accuracy with processing throughput. This periodic approach ensures voltage offsets remain accurate enough to prevent bit errors while minimizing interruptions to normal memory operations, thereby maintaining productivity.
Data Source
AI summary
A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device initializes a block family associated with the memory device and initializes a timer associated with the block family. In response to the timer reaching a soft closure value, the processing device performs a soft closure of the block family while programming a block, determines an amount of time until filling the block completely with data being received from a host system, and decides whether to finish programming the block based on the amount of time and a remainder of time left until the timer reaches a hard closure value.