Block Family Scan Management for Memory Subsystems

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Solution Overview

Problem

Existing memory sub-systems face increased bit error rates due to temporal voltage shift caused by slow charge loss in memory cells, which current technologies inadequately address, leading to inefficient strategies and high error rates.

Innovation Solution

Implementing a block family-based error avoidance strategy that combines block families with similar data state metrics through a combination scan process, which can start and stop based on predefined conditions to efficiently manage the number of block families and minimize overhead, thereby reducing bit error rates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If block families are tracked individually with separate metadata, then voltage distribution accuracy is improved, but metadata table size and memory overhead increase

Engineering Contradiction:
Improvevoltage distribution tracking accuracyVSAvoidmetadata table size
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent merges multiple block families into a single combined block family when their voltage distributions are similar. Instead of maintaining separate metadata entries for each block family, the system combines them and uses a single metadata entry to represent the merged group, thereby reducing metadata table size while preserving voltage distribution tracking accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a universal metadata entry that can represent multiple block families with similar characteristics. This multi-functional metadata structure serves both individual block families and their merged combinations, eliminating the need for separate dedicated metadata entries for each block family and reducing overall memory overhead.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If combination scan process continuously merges block families, then bit error rate is reduced, but processing overhead and time consumption increase

Engineering Contradiction:
Improvebit error rateVSAvoidscan process time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent implements periodic combination scan processes instead of continuous scanning. The system performs scans at predetermined intervals or when specific conditions are met (such as when metadata table usage exceeds a threshold), thereby reducing the frequency of scan operations and minimizing time loss while still maintaining reliable error avoidance.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The system uses feedback mechanisms to trigger combination scans only when necessary. By monitoring metadata table usage, voltage distribution similarities, and error rates, the system intelligently determines when to initiate scans, avoiding unnecessary processing time while ensuring errors are corrected when they become significant.

Inventive Principle:
Principle #23Feedback

3Manufacturing precision

If more block families are maintained separately, then voltage distribution granularity is improved, but scan process complexity increases

Engineering Contradiction:
Improvevoltage distribution granularityVSAvoidscan process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments block families into groups based on their voltage distribution characteristics. By organizing block families into voltage bins or ranges and only scanning within similar groups, the system maintains fine-grained voltage distribution tracking while reducing the overall complexity of the scan process through structured organization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different scanning strategies to different voltage distribution groups. Instead of uniformly scanning all block families with the same complexity, the system tailors scan processes to local characteristics of each voltage group, simplifying scans for well-behaved groups while maintaining detailed scrutiny only where needed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11941277B2Combination scan management for block families of a memory device
Publication Date: 2024.03.26 MICRON TECHNOLOGY INC
  • US11941277B2 patent drawing
  • US11941277B2 patent drawing
  • US11941277B2 patent drawing

AI summary

An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan process on a plurality of block families of the memory device; responsive to determining, based on the scan process, that a first block family of the plurality of block families and a second block family of the plurality of block families meet a combining criterion, merge the first block family and the second block family; and responsive to determining that a terminating condition has been satisfied, terminate the scan process.