Block Floating Point Normalization Circuit with Segmented Precision
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Solution Overview
Problem
Existing arithmetic processing apparatuses for block floating point processing face challenges with large circuit scale and reduced precision due to the need for extensive memory to hold all data before normalization and rounding, and normalization with a common exponent, which can lead to reduced precision when dealing with a wide dynamic range of values.
Innovation Solution
The apparatus includes a first normalization circuit that normalizes data with a common exponent in each cycle, followed by a rounding circuit to reduce bit width, and a second normalization circuit that further normalizes the rounded data with a common exponent based on maximum exponents, allowing for efficient storage and processing of data with reduced memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all data in a block are held in memory before normalization processing, then the normalization can be performed with a common exponent, but the memory capacity and circuit scale become large
Solution Approach 1:
The block floating point data processing is divided into two stages: first normalization processing performed on input data before storage, and second normalization processing performed on rounded data after storage. This segmentation allows different normalization operations at different stages, reducing the need to hold all original data in memory while maintaining precision.
Solution Approach 2:
The first normalization processing is performed preliminarily on the input block floating point data before the data is stored in memory. This preliminary normalization reduces the dynamic range of values, allowing efficient storage with reduced memory capacity while preserving the information needed for subsequent precision-critical operations.
2Device complexity
If block floating point data with wide dynamic range are normalized with a common exponent, then the normalization is simple, but the precision is reduced
Solution Approach 1:
The normalization process is segmented into two distinct operations: first normalization processing that applies a common exponent to reduce complexity, and second normalization processing that applies individual exponents to maintain precision. This segmentation resolves the contradiction by distributing the complexity-precision tradeoff across two stages.
Solution Approach 2:
The exponent parameter is changed differently at different stages: in the first normalization, a common exponent is applied to all data in the block, simplifying the normalization circuit. In the second normalization, individual exponents are applied to rounded data, maintaining precision. This parameter change strategy resolves the contradiction between simplicity and precision.
3Device complexity
If rounding processing is performed after holding all data in memory, then the bit width is reduced, but the memory requirements increase the circuit scale
Solution Approach 1:
Rounding processing is performed as a preliminary action after first normalization but before second normalization. This timing allows the rounded data to be stored in memory with reduced bit width, decreasing memory capacity requirements while still allowing precision-critical second normalization to operate on the rounded values.
Data Source
AI summary
Provided is an arithmetic processing apparatus and an arithmetic processing method which can perform block floating point processing with small circuit scale and high precision.A first normalization circuit (120) performs a first normalization, in which a plurality pieces of data, which have a common exponent and which are either fixed-point number representation data or mantissa portion data of block floating-point number representation, are inputted in each of a plurality of cycles and the plurality of pieces of data inputted in each of the plurality of cycles are respectively normalized with the common exponent on the basis of a maximum exponent for the plurality of pieces of data inputted in a corresponding one of the plurality of cycle. A rounding circuit (130) outputs a plurality of pieces of rounded data which are obtained by reducing a bit width of respective one of the plurality of pieces of data on which the first normalization is performed. A first storage circuit (140) stores a plurality of pieces of rounded data regarding the plurality of cycles in which the first normalization is performed and outputs a plurality of designated pieces of rounded data among the stored plurality of pieces of rounded data. A second normalization circuit (150) performs a second normalization, in which the plurality of designated pieces of rounded data are respectively normalized with an exponent which is common to the plurality of designated pieces of rounded data on the basis of the maximum exponents used in the first normalization for the plurality of designated pieces of rounded data and a maximum value of the maximum exponents, and outputs a result of the second normalization.