Block Interleaving with Sequential Indexing for Lower Hardware Complexity
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Solution Overview
Problem
Existing data transceiving systems face inefficiencies in terms of hardware area complexity and power consumption due to high computational complexity in block interleaving methods, particularly for right angle isosceles triangle-shaped blocks.
Innovation Solution
A method and apparatus for block-based interleaving that generates input and output indices for sub-blocks using a sequential relationship, allowing for simple calculations and reduced hardware complexity, thereby improving power efficiency and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional block interleaving methods are used for right angle isosceles triangle-shaped blocks, then error correction performance is improved, but hardware area complexity and power consumption increase
Solution Approach 1:
The interleaver divides the right angle isosceles triangle-shaped block into multiple sub-blocks arranged in a matrix structure. This segmentation allows the system to process smaller, more manageable units while maintaining the overall error correction functionality, thereby reducing hardware complexity without sacrificing reliability.
Solution Approach 2:
The patent changes the computational parameters by introducing a sequential relationship for generating input and output indices of sub-blocks. Instead of complex calculations, the system uses simple sequential increments (e.g., adding 1 to the previous index), which significantly reduces hardware area complexity and power consumption while preserving error correction performance.
2Reliability
If traditional block interleaving methods are used for right angle isosceles triangle-shaped blocks, then error correction performance is improved, but power consumption increases
Solution Approach 1:
The patent transforms the power-consuming complex index calculation process into a simple sequential parameter generation process. By using sequential relationships (e.g., current index = previous index + 1) instead of mathematical computations, the system dramatically reduces power consumption while maintaining the same error correction performance.
Solution Approach 2:
The patent extracts and eliminates the computationally intensive parts of the traditional interleaving algorithm. By separating the essential function (error correction through interleaving) from the complex calculation mechanism, the system achieves the same reliability with minimal power consumption using simple sequential index generation.
3Device complexity
If sequential relationship method is used to generate input and output indices, then hardware area complexity is reduced, but computational complexity may increase
Solution Approach 1:
The patent changes the nature of computation from complex mathematical calculations to simple sequential parameter generation. The sequential relationship method uses basic arithmetic operations (adding 1 to previous index values) which are computationally efficient and can be executed rapidly, thereby improving productivity while reducing hardware area complexity.
Data Source
AI summary
An apparatus includes an encoder configured to encode source data and generate a codeword composed of a plurality of bits, and an interleaver configured to perform, on the codeword, block-based interleaving including a plurality of sub-blocks, wherein the interleaver is configured to generate a first reference input index of a first reference sub-block from among the sub-blocks, generate, based on the first reference input index, a first input index of a first sub-block from among the sub-blocks, the first sub-block being arranged to be adjacent to the first reference sub-block in a first direction, and store, in an internal memory, bits corresponding to the first reference sub-block and the first sub-block, according to the first reference input index and the first input index, respectively.