Block Interleaving with Sub-Block Indexing for Lower Hardware Complexity
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Solution Overview
Problem
Existing block interleaving methods for data transmission face challenges with high computational complexity, leading to inefficiencies in power consumption and hardware area complexity.
Innovation Solution
A method and apparatus for performing block-based interleaving using sub-blocks, where an interleaver generates reference input indices for sub-blocks and calculates input indices for adjacent sub-blocks, reducing computational complexity and improving power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional block interleaving is performed on the entire codeword, then error correction performance is improved, but computational complexity and hardware area increase
Solution Approach 1:
The patent divides the codeword into multiple sub-blocks and performs interleaving operations on each sub-block separately. This segmentation allows the interleaving process to be distributed across multiple smaller units, reducing the computational complexity and hardware resources required for each individual operation while maintaining the overall error correction performance through the collective effect of all sub-block interleavings.
2Reliability
If traditional block interleaving is performed on the entire codeword, then error correction performance is improved, but power consumption increases
Solution Approach 1:
By segmenting the codeword into sub-blocks and processing them independently, the patent reduces the power consumption associated with large-scale interleaving operations. Each sub-block requires less computational power, and the distributed processing approach allows for more efficient resource utilization, thereby reducing overall power consumption while achieving the same error correction performance.
Solution Approach 2:
The patent applies interleaving selectively to sub-blocks rather than uniformly to the entire codeword. This partial action approach focuses computational resources on specific segments where interleaving provides the most benefit, avoiding unnecessary processing in other areas and thus reducing overall power consumption while maintaining adequate error correction performance.
3Device complexity
If sequential index generation for adjacent sub-blocks is used, then hardware complexity is reduced, but processing time may increase
Solution Approach 1:
The patent generates reference input indices for sub-blocks in advance and uses these as a basis for calculating indices of adjacent sub-blocks. This preliminary action of establishing reference points before full processing allows for more efficient sequential generation of indices, reducing the computational overhead during the main interleaving process and thereby minimizing processing time delays.
Data Source
AI summary
An apparatus includes an encoder configured to encode source data and generate a codeword composed of a plurality of bits, and an interleaver configured to perform, on the codeword, block-based interleaving including a plurality of sub-blocks, wherein the interleaver is configured to generate a first reference input index of a first reference sub-block from among the sub-blocks, generate, based on the first reference input index, a first input index of a first sub-block from among the sub-blocks, the first sub-block being arranged to be adjacent to the first reference sub-block in a first direction, and store, in an internal memory, bits corresponding to the first reference sub-block and the first sub-block, according to the first reference input index and the first input index, respectively.