Block-Kronecker QC-LDPC Structure for 3888-Bit 2/3 Code Blocks
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Solution Overview
Problem
Current communication systems using LDPC codes are limited by the longest block length supported in 802.11 standards, which restricts error correction capabilities and achievable gains in radio channels.
Innovation Solution
The development of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a block length of 3888 bits and a code rate of 2/3, which doubles the block length of the longest code supported in 802.11 standards, enabling more efficient encoding and decoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the block length of LDPC code is increased beyond 1944 bits (current 802.11 standard limit), then error correction capability and communication reliability are improved, but system complexity and implementation difficulty increase
Solution Approach 1:
The patent divides the large block length LDPC code into multiple smaller code blocks that can be processed independently. Specifically, a code block of length 3888 bits is segmented into two sub-blocks of 1944 bits each, allowing the system to achieve enhanced error correction capability while maintaining manageable processing complexity through parallel or sequential decoding of smaller units.
Solution Approach 2:
The patent employs a nested structure where a larger LDPC code block contains multiple smaller code blocks. The outer code block of 3888 bits encompasses inner code blocks of 1944 bits, creating a hierarchical coding structure that enables both improved reliability through longer overall block length and reduced complexity by reusing decoding algorithms designed for the smaller inner blocks.
2Reliability
If a new LDPC code with block length 3888 bits is developed, then communication gains in radio channels are improved, but compatibility with existing 802.11 standards is reduced
Solution Approach 1:
The patent designs the 3888-bit LDPC code to serve multiple functions: it can operate as a complete standalone code block for enhanced performance applications, and it can be divided into two 1944-bit sub-blocks that are fully compatible with existing 802.11 standards. This multi-functionality allows the system to achieve communication gains when needed while maintaining backward compatibility with legacy systems.
Solution Approach 2:
The patent introduces dynamic adaptability by allowing the system to flexibly choose between using the full 3888-bit code block or splitting it into 1944-bit sub-blocks based on channel conditions and compatibility requirements. This dynamic approach enables the system to optimize performance when compatibility is not a constraint while seamlessly falling back to standard-compliant operation when needed.
Data Source
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AI summary
An apparatus may include a transmitter (120) and one or more processors (2010). The one or more processors (2010) may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check, QC-LDPC, code according to a code rate of 2/3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors (2010) may encode data using the second parity check matrix. The transmitter (120) may be configured to transmit the encoded data.