Block-Kronecker QC-LDPC Matrices for 3888-Bit 2/3 Coding
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Solution Overview
Problem
Existing wireless communication standards, such as IEEE 802.11n-802.11be, are limited by a block length of 1944 bits, which restricts the gain in radio channels, particularly in 2×2 multiple-input and multiple-output channels, and the encoding and decoding processes for LDPC codes are computationally intensive due to high-density generator matrices.
Innovation Solution
The implementation of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a block length of 3888 bits and a code rate of 2/3, utilizing a parity check matrix with a quasi-cyclic structure, allows for efficient encoding and decoding through the use of a binary matrix and Khatri-Rao lifting to generate a parity check matrix, enabling parallel decoding and re-use of mother codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the block length of LDPC code is increased beyond the standard limit, then the gain in radio channels and error correction capabilities are improved, but the device complexity and computational intensity increase
Solution Approach 1:
The patent segments the LDPC code into two distinct parts: a first LDPC code with block length up to 1944 bits and a second LDPC code with block length greater than 1944 bits. This segmentation allows the system to handle longer block lengths by dividing them into manageable segments, thereby improving error correction capabilities while controlling computational complexity through structured processing of each segment separately
Solution Approach 2:
The patent introduces a new dimension by defining a second LDPC code with block length exceeding the standard 1944-bit limit. This extends the traditional single-dimension block length constraint into a multi-dimensional code structure, enabling longer block lengths (e.g., 3888 bits or more) to be processed efficiently by leveraging the modular relationship between the first and second codes
2Reliability
If the block length of LDPC code is doubled to 3888 bits, then the gain in 2×2 MIMO channels reaches about 2 dB, but the encoding and decoding computational complexity increases
Solution Approach 1:
The patent applies preliminary action by first establishing the first LDPC code with block length up to 1944 bits as a foundation, then building the second LDPC code with extended block length based on this established structure. This preliminary coding framework enables the system to achieve 2 dB gain in 2×2 MIMO channels while managing computational intensity through the hierarchical code construction approach
3Reliability
If parity bits are generated using a complex process, then error correction capabilities are improved, but the encoding time and processing delay increase
Solution Approach 1:
The patent segments the parity bit generation process into two phases: first generating parity bits for the first LDPC code with block length up to 1944 bits, then generating additional parity bits for the second LDPC code with extended block length. This segmentation reduces encoding time by processing parity generation in manageable stages rather than as a single complex operation, while maintaining improved error correction capabilities
Data Source
AI summary
An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 2/3, a second parity check matrix corresponding to a first exponent matrix comprising 768 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.