Block-Kronecker QC-LDPC Coding for Longer 5/6 Wi-Fi Blocks

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Solution Overview

Problem

Current communication systems using LDPC codes are limited by the longest block length supported in 802.11 standards, which restricts the gain in radio channels, especially in 2×2 MIMO channels.

Innovation Solution

The implementation of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a block length of 3888 bits and a code rate of 5/6, which doubles the block length of the longest code supported in 802.11n-802.11be standards, enhancing encoding and decoding efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the block length of LDPC code is increased beyond the standard limit, then the gain in radio channels and error correction capability is improved, but the device complexity and computational complexity increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the large block length LDPC code into smaller sub-blocks that can be processed independently. The encoding and decoding operations are segmented into manageable units, reducing the computational burden while maintaining the overall error correction capability of the extended block length code.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the problem from a single large matrix operation into multiple smaller matrix operations by introducing a block structure. This dimensional change allows the system to achieve the benefits of long block length (improved reliability) while avoiding the prohibitive computational complexity through structured sub-block processing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If the block length of LDPC code is doubled to 3888 bits, then the gain in 2×2 MIMO channels reaches about 2 dB, but the encoding and decoding computational complexity increases

Engineering Contradiction:
Improvegain in radio channelsVSAvoidencoding and decoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the 3888-bit block into smaller sub-blocks that can be encoded and decoded separately. This segmentation maintains the error correction performance and 2 dB gain in MIMO channels while reducing the computational complexity by avoiding single large matrix operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the structural parameters of the LDPC code by introducing a specific block structure with defined sub-block sizes and arrangements. This parameter change enables the system to achieve extended block length benefits while controlling computational complexity through the structured design.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If standard LDPC codes are used in 802.11n-802.11be standards, then compatibility is maintained, but the block length limitation restricts the gain in radio channels

Engineering Contradiction:
Improvecompatibility with standardsVSAvoidgain in radio channels
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces dynamic adaptability by providing a configurable block structure that can operate with different block lengths. The system can maintain compatibility with standard block lengths when required while dynamically switching to extended block lengths (3888 bits) when improved radio channel performance is needed, achieving both compatibility and enhanced reliability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250202504A1Systems and methods for block-kronecker based low density parity check (LDPC) code with 5/6 code rate
Publication Date: 2025.06.19 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US20250202504A1 patent drawing
  • US20250202504A1 patent drawing
  • US20250202504A1 patent drawing

AI summary

An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5/6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.