Block-Kronecker QC-LDPC Code Layout for 3888-Bit MIMO Gain

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Solution Overview

Problem

Current communication systems using LDPC codes are limited by the longest block length supported in 802.11 standards, which restricts the gain achievable in radio channels, particularly in 2x2 MIMO channels.

Innovation Solution

The implementation of a quasi-cyclic-low-density parity-check (QC-LDPC) code with a block length of 3888 bits and a code rate of 3/4, which doubles the block length of the longest code supported in 802.11n-802.11be standards, enabling more efficient encoding and decoding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the block length of LDPC code is increased beyond 1944 bits (current 802.11 standard limit), then the coding gain in radio channels is improved, but the complexity of encoding and decoding processes increases

Engineering Contradiction:
Improvecoding gainVSAvoidencoding and decoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the large block length LDPC code into multiple smaller code blocks that are processed in parallel. Specifically, a 3888-bit code is divided into two 1944-bit code blocks, each processed by separate encoding/decoding units. This maintains the benefits of long block length coding while reducing the complexity of individual processing units and enabling parallel implementation.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs nesting by incorporating multiple code blocks within a single transmission frame structure. The outer code (3888 bits) contains inner codes (1944 bits each), creating a hierarchical structure where smaller code units are nested within larger code structures. This allows the system to achieve long block length performance while using standardized smaller code building blocks.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If a new LDPC code with block length 3888 bits is implemented, then the gain in 2x2 MIMO channels is improved, but compatibility with existing 802.11 standards is reduced

Engineering Contradiction:
ImproveMIMO channel performanceVSAvoidstandard compatibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent achieves universality by designing the 3888-bit LDPC code to be constructed from standardized 1944-bit code blocks defined in 802.11 standards. The encoding and decoding processes reuse existing standard-compliant components, allowing the system to maintain compatibility with current standards while achieving enhanced performance through the extended block length configuration.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges multiple 1944-bit standard-compliant code blocks to form a 3888-bit code structure. By combining standardized building blocks in a specific configuration with defined parity bit relationships, the system achieves improved MIMO performance while maintaining adherence to existing standard specifications through the use of recognized code structures.

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If the code block length is doubled from 1944 to 3888 bits, then the error correction capability is improved, but the processing time increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent reduces processing time by segmenting the 3888-bit code into two independent 1944-bit code blocks that can be encoded and decoded in parallel. This segmentation allows multiple processing units to work simultaneously on different code blocks, effectively reducing the overall processing time compared to sequential processing of a single large block, while maintaining the error correction benefits of the extended block length.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP4572153A1Systems and methods for block-kronecker based low density parity check (LDPC) code with 3/4 code rate and code block length 3888 bits
Publication Date: 2025.06.18 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • EP4572153A1 patent drawingFigure 1
  • EP4572153A1 patent drawingFigure 2
  • EP4572153A1 patent drawingFigure 3

AI summary

An apparatus may include a transmitter (120) and one or more processors (2010). The one or more processors (2010) may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 3/4, a second parity check matrix corresponding to a first exponent matrix comprising 576 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter (120) may be configured to transmit the encoded data.