Block Level Design for Multi-Die Timing Closure
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Solution Overview
Problem
Current Electronic Design Automation (EDA) tools face limitations in handling the complexity of multi-layer die structures and 3-D stacking designs, leading to challenges in ensuring proper functionality and timing closure across multiple dies, which can overwhelm existing infrastructure and reduce the benefits of advanced microelectronic designs.
Innovation Solution
The approach involves designing integrated circuits at the block level, where repeatable functional blocks are identified and designed using a Process Design Kit (PDK) to span across multiple dies, ensuring timing closure at the block level, and then instantiating these blocks across individual dies to be stacked, thereby simplifying the design process and reducing the complexity for EDA tools.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If EDA tools are used to design and configure multi-layer die structures and 3-D stacking, then functionality and timing closure can be ensured, but the complexity and size of EDA databases exceed the capabilities of existing EDA infrastructure
Solution Approach 1:
The patent divides the EDA design process into two distinct phases: a high-level block-level design phase that defines functional blocks spanning multiple dies, and a detailed die-level design phase that instantiates these blocks. This segmentation reduces the complexity of individual EDA databases by working with abstract block representations rather than detailed transistor-level designs, thereby maintaining reliability while reducing infrastructure requirements.
Solution Approach 2:
The patent introduces a new design dimension at the block level that spans multiple dies, transitioning from traditional single-die EDA design to multi-die block-level design. This dimensional shift allows EDA tools to manage complexity by operating at a higher abstraction level where functional blocks are defined independently of specific die implementations, reducing the burden on EDA databases.
2Adaptability or versatility
If 3-D stacking is used to increase storage capacity and functionality, then performance and capacity requirements are met, but the design complexity and manufacturing/testing challenges become too much for EDA databases and users
Solution Approach 1:
The patent segments the 3-D stacked die structure into repeatable functional blocks that can be independently designed and then instantiated across multiple dies. This segmentation allows the complex 3-D stacking configuration to be managed through modular block definitions rather than monolithic design approaches, reducing the cognitive and computational burden on EDA users while maintaining the versatility and capacity benefits of 3-D stacking.
Solution Approach 2:
The patent creates universal functional blocks that can be instantiated across different die levels and configurations. These blocks serve multiple functions: defining timing relationships, establishing functional connectivity, and providing a template for detailed die-level design. This universality reduces the need for separate design approaches for each 3-D stacking configuration, thereby reducing overall design complexity while maintaining adaptability.
3Ease of operation
If manual design and configuration is used for simple IC structures, then ease of design is maintained, but the ability to handle complex configurations with billions of transistors is insufficient
Solution Approach 1:
The patent segments the IC design process into automated block-level definition and manual die-level instantiation. The automated block-level phase handles the complex configuration of billions of transistors through functional block definitions, while manual intervention is required only for final die-level customization. This segmentation maintains ease of operation for high-level design while enabling handling of complex IC structures.
Solution Approach 2:
The patent introduces functional blocks as intermediary elements between the high-level design requirements and the detailed transistor implementation. These blocks serve as mediators that translate complex functional requirements into manageable design templates, reducing the direct cognitive burden on designers while enabling them to handle complex IC structures systematically.
Data Source
AI summary
An integrated circuit and a method for designing an IC where the smallest repeatable block is selected, designed and tested to span across multiple die levels. The block is configured to be timing closed at the block level thereby reducing the overall complexity of the design and avoiding the limiting effects of the constrained EDA tools. The block may subsequently be repeated on multiple die to be stacked in an IC.