Block-Level RC Extraction via Full-Chip Domain Translation
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Solution Overview
Problem
Current full-chip modeling approaches for integrated circuits are limited to the sign-off stage and cannot be utilized early in the design implementation flow due to the lack of full-chip information and sufficient time for long simulations, preventing accurate resistance and capacitance extraction, especially at the block level where each IP or macro block is implemented independently.
Innovation Solution
A method and system that translate full-chip design domain information to a block-level design domain, allowing model-based prediction results to be used for parasitic RC and timing extractions, enabling early design implementation flow by converting manufacturing variation models like CMP and etch models into block-level coordinates for localized analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If full-chip modeling approaches are used for RC extraction, then manufacturing variation accuracy is improved, but design flow timing and computational efficiency deteriorate
Solution Approach 1:
The patent divides the full-chip design into independent macro blocks, allowing RC extraction to be performed at the block level rather than requiring complete full-chip information. This segmentation enables earlier execution of RC extraction during design implementation while maintaining accuracy by considering manufacturing variations specific to each block's context.
Solution Approach 2:
The patent performs RC extraction with manufacturing variation modeling at the macro block level before complete full-chip design finalization. By conducting preliminary RC extraction on individual blocks with estimated manufacturing contexts, designers can make informed decisions earlier in the design flow without waiting for complete full-chip modeling results.
2Manufacturing precision
If full-chip information is available for modeling, then manufacturing variation prediction accuracy is improved, but design flexibility and early implementation capability deteriorate
Solution Approach 1:
The patent applies local quality by considering manufacturing variations specific to each macro block's local context rather than applying uniform full-chip models. Each block can be analyzed with manufacturing parameters relevant to its specific location and characteristics, enabling early design flexibility while maintaining manufacturing accuracy.
3Measurement precision
If long simulations are performed for accurate RC extraction, then extraction precision is improved, but productivity and design iteration speed deteriorate
Solution Approach 1:
By segmenting the design into macro blocks, the patent enables parallel processing of RC extraction for multiple blocks independently. This reduces overall computation time compared to sequential full-chip analysis, improving design iteration speed while maintaining extraction precision through block-level manufacturing variation modeling.
Data Source
AI summary
A method, system, and computer program product are disclosed for performing RC extraction from the perspective of the block level. A translation mechanism is employed to convert from a full-chip design domain to a block-level design domain. This allows model-based prediction results to be used in the early design implementation flow when parasitic RC and timing extractions are performed, where the model-based prediction results relate to predictions of manufacturing variations such as thickness and topography.