File System Block Mapping Bypass for Low-Latency Erasure-Coded Writes

The patent segments the address mapping function into two distinct layers: a first layer mapping (L1) that maps logical addresses to intermediate addresses, and a second layer mapping (L2) that maps intermediate addresses to physical addresses. This segmentation allows the system to bypass the L2 mapping for sequential writes by directly using L1, thereby reducing I/O latency while maintaining data reliability through the preserved L2 mapping structure for fault tolerance.

The patent performs preliminary action by pre-allocating intermediate addresses through the first layer mapping before actual data writing occurs. The L1 mapping is established in advance and can be directly used for sequential writes without requiring real-time L2 lookup, thus reducing I/O latency while the L2 mapping remains available for reliability operations.

The patent applies partial action by allowing sequential writes to proceed using only the first layer mapping without requiring complete stripe formation or full second layer mapping updates. This partial approach reduces the write amplification factor from 3x (read-modify-write) to接近1x for sequential writes, while fault tolerance is maintained through the underlying erasure coding structure and the preserved L2 mapping for recovery operations.

The patent extracts the address mapping overhead from the write path by separating L1 and L2 mappings. The L2 mapping is extracted out of the critical write path, allowing writes to use only L1 mapping, thus reducing write amplification. The L2 mapping remains intact for fault tolerance operations, achieving both goals simultaneously.