Block Mask Register Packet Classification via Compiled Trie Traversal

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Solution Overview

Problem

Current packet classification methods are inefficient in handling the increasing complexity and bandwidth demands of network applications, requiring novel solutions that can handle diverse rule sets without significant performance loss, and are not well-suited to advanced hardware and software technologies.

Innovation Solution

The method involves compiling data structures to process keys associated with a block mask register (BMR) by identifying and masking specific fields of rules, building data structures to traverse rules, and enabling a search processor to mask fields based on the BMR, allowing for efficient packet classification and processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If traditional packet classification methods are used to handle increasing network complexity and bandwidth demands, then packet classification functionality is maintained, but processing efficiency and performance deteriorate

Engineering Contradiction:
Improvepacket classification efficiencyVSAvoidnetwork application complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments packet classification into multiple independent BMRs (Block Mask Registers), each handling specific field combinations. This segmentation allows parallel processing of different classification tasks, improving overall efficiency while managing complexity through modular organization of classification rules.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent pre-compiles data structures (tries) for each BMR configuration before packet processing occurs. By preparing the classification paths in advance, the system eliminates runtime compilation overhead and achieves fast, deterministic packet classification without sacrificing performance for handling network complexity.

Inventive Principle:
Principle #10Preliminary action

2Speed

If memory-intensive solutions like TCAMs are used for packet classification, then classification speed is improved, but memory resources are consumed excessively

Engineering Contradiction:
Improvepacket processing speedVSAvoidmemory resources
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent replaces hardware-based TCAM (Ternary Content-Addressable Memory) with a software-based trie data structure compiled for each BMR. This substitution maintains fast packet processing speeds through efficient trie traversal while using standard memory resources, avoiding the excessive memory consumption associated with TCAM implementations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Adaptability or versatility

If comprehensive field masking is applied to handle diverse rule sets, then adaptability is improved, but processing time increases

Engineering Contradiction:
Improverule set flexibilityVSAvoidprocessing time
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent dynamically configures BMRs to mask different field combinations based on the specific rule set being processed. Each BMR can be independently configured to handle different field masking requirements, allowing the system to adapt to diverse rule sets while maintaining fast processing by only masking necessary fields rather than all fields comprehensively.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9647947B2Block mask register key processing by compiling data structures to traverse rules and creating a new rule set
Publication Date: 2017.05.09 MARVELL ASIA PTE LTD
  • US9647947B2 patent drawing
  • US9647947B2 patent drawing
  • US9647947B2 patent drawing

AI summary

A packet classification system, methods, and corresponding apparatus are provided for enabling packet classification. A processor of a routing appliance coupled to a network compiles data structures to process keys associated with a particular block mask register (BMR) of a plurality of BMRs. For each BMR of the plurality of BMRs, the processor identifies at least one of or a combination of: i) at least a portion of a field of a plurality of rules and ii) a subset of fields of the plurality of fields to be masked. The processor also builds at least one data structure used to traverse a plurality of rules based on the identified at least one of or a combination of: i) at least a portion of a field of a plurality of rules and ii) a subset of fields of the plurality of fields to be masked.