Block Memory Layout Between Logic Tiles for Scalable FPGA I/O
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Solution Overview
Problem
Existing integrated circuit designs for programmable logic ICs do not effectively utilize memory resources by integrating memory arrays between or adjacent to logic tiles, limiting the efficiency of data input/output operations and interconnectivity.
Innovation Solution
Incorporating one or more arrays of block memory, such as SRAM, DRAM, Flash, EPROM, EEPROM, or MRAM, between or adjacent to logic tiles in the programmable/configurable logic circuitry, utilizing unused I/O pins for memory I/O connections to enhance tile-to-tile communication and memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of logic elements are integrated into a single integrated circuit, then the functionality and processing power are improved, but heat dissipation becomes a limiting factor that restricts further integration
Solution Approach 1:
The patent divides the logic circuit into multiple independent logic blocks (first logic block, second logic block, etc.) that are spatially separated and can be independently controlled. Each logic block has its own set of sense amplifiers and memory cells, allowing localized heat management and preventing heat accumulation across the entire circuit.
2Area of stationary object
If logic circuits are designed with high integration density, then the area occupied is reduced, but the complexity of signal routing and interference management increases
Solution Approach 1:
The patent extracts the sense amplifier function from the traditional memory cell structure and places it as a separate component adjacent to each logic block. This separation allows independent optimization of the sense amplifiers and reduces the complexity of signal routing within densely integrated memory cells.
Solution Approach 2:
The patent introduces a third dimension by stacking multiple logic blocks and memory blocks vertically, with interlayer connection lines connecting corresponding nodes across different layers. This vertical arrangement reduces the planar area required while maintaining signal integrity and reducing routing complexity.
3Area of stationary object
If conventional sense amplifier circuits are used in highly integrated logic circuits, then the circuit area is reduced, but power consumption increases and logic element performance deteriorates
Solution Approach 1:
The patent implements different sense amplifier designs for different logic blocks based on their specific requirements. Each sense amplifier is optimized for its local context, with parameters such as transistor size, threshold voltage, and circuit topology tailored to the specific logic block it serves, thereby reducing overall power consumption while maintaining area efficiency.
Data Source
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AI summary
An integrated circuit comprising programmable/configurable logic circuitry including a plurality of logic tiles, arranged in an array, wherein each logic tile includes logic circuitry and I/O connected in an interconnect network via multiplexers. A first logic tile includes (i) a first portion of a perimeter which forms at least a portion of the periphery of the programmable/configurable logic circuitry and (ii) a second portion of a perimeter which is interior to such circuitry's periphery, wherein memory I/O is disposed on the second portion of the perimeter of the first logic tile. A second logic tile includes a second portion of a perimeter which is interior to the programmable/configurable logic circuitry's periphery and opposes the first logic tile's perimeter. Memory array(s), located between the second portions of the perimeters of the first and second logic tiles, is/are coupled to memory I/O of at least the first logic tile.