Block Model to HDL Translation for Circuit Design
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Solution Overview
Problem
Current block-based circuit design tools require extensive knowledge of target hardware and limit optimization opportunities, making it difficult for designers without expertise in RTL to create efficient circuit designs.
Innovation Solution
A design tool that converts block models into high-level language (HLL) specifications, allowing for hardware optimization directives to be inserted, and then generates hardware description language (HDL) specifications for circuit implementation, enabling designers with little hardware experience to create optimized integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If block-based modeling tools are used for circuit design, then ease of operation is improved, but device complexity increases and manufacturing precision deteriorates
Solution Approach 1:
The patent introduces an intermediary translation system that converts block-based design models into precise hardware description language (HDL) code through multiple passes: a semantic analysis pass that understands block semantics and relationships, and a code generation pass that produces synthesizable HDL. This intermediary translation layer bridges the gap between high-level block modeling and low-level circuit implementation, maintaining both ease of operation and manufacturing precision.
Solution Approach 2:
The translation process is segmented into distinct passes: semantic analysis pass for understanding block models and their relationships, code generation pass for producing HDL code, and optimization pass for performance enhancement. This segmentation allows each pass to specialize in specific tasks, ensuring both ease of block-based design and precision of circuit implementation.
2Ease of operation
If block-based modeling tools are used for circuit design, then ease of operation is improved, but productivity deteriorates due to slow simulation
Solution Approach 1:
The patent performs preliminary semantic analysis on block models to understand their semantics, relationships, and intended behavior before code generation. This preliminary action allows the system to optimize the generated HDL code for faster simulation and synthesis, rather than generating basic code and optimizing later. The semantic analysis pass identifies optimization opportunities upfront, improving productivity while maintaining ease of block-based design.
Solution Approach 2:
The translation system dynamically adapts its code generation strategy based on the semantic characteristics of the block model. Different block types and relationships trigger different optimization techniques in the code generation pass, allowing the system to maintain high productivity across diverse design scenarios while preserving the simplicity of block-based modeling.
3Ease of operation
If designers use block-based modeling tools with limited data type support, then ease of operation is improved, but adaptability deteriorates
Solution Approach 1:
The patent creates a universal translation framework that handles multiple data types (scalars, vectors, matrices, custom types) through a unified semantic analysis approach. The semantic analysis pass identifies the specific data type and characteristics of each block, and the code generation pass applies appropriate HDL representations and optimizations for each type. This universal approach maintains ease of block-based operation while achieving broad adaptability across different data types and hardware targets.
4Manufacturing precision
If designers need knowledge of target hardware and RTL for effective block-based design, then manufacturing precision is improved, but ease of operation deteriorates
Solution Approach 1:
The patent implements a self-service translation system where the block model semantics automatically guide the HDL code generation process without requiring designer intervention or expertise. The semantic analysis pass extracts all necessary information from the block model, and the code generation pass automatically produces optimized, synthesizable HDL code that is tailored to the target hardware architecture. This self-service approach maintains manufacturing precision while dramatically improving ease of operation for designers without hardware expertise.
Data Source
AI summary
A design tool executing on a computer system converts a block model of a circuit design to a high-level language (HLL) specification. The design tool then converts the HLL specification to a hardware description language (HDL) specification. Circuit implementation data is generated from the HDL specification by the design tool, and the circuit implementation data can be used to make an integrated circuit that performs functions specified by the circuit design.