Block RAM Address Arithmetic for FPGA Routing Congestion
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Solution Overview
Problem
Conventional Field Programmable Gate Array (FPGA) implementations face challenges in reducing routing congestion and power consumption due to the need to route multiple address lines to multiple embedded memory blocks, which also leads to critical timing delays.
Innovation Solution
Incorporating address arithmetic capabilities into block RAMs, allowing for incremental address handling within the RAMs, reducing the need for explicit address routing and enabling efficient access to wide memories and FIFOs with a single address bus, and facilitating burst access without explicit address supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple address lines are routed to each block RAM in a group, then each block RAM can be individually addressed, but routing congestion increases and power consumption increases
Solution Approach 1:
The patent merges the addressing function from multiple separate address lines into a single shared address bus. By combining individual addressing capabilities into a unified addressing scheme where a single address bus controls multiple block RAMs through decoding logic, the patent reduces routing congestion while maintaining the ability to individually address each block RAM in the group.
Solution Approach 2:
The single shared address bus serves multiple functions by being able to address any block RAM in the group through decoding. The universal address bus can be configured to access different block RAMs based on the address value, providing multi-functionality without requiring separate dedicated address lines for each memory block.
2Adaptability or versatility
If multiple address lines are routed to each block RAM in a group, then each block RAM can be individually addressed, but power consumption increases due to toggling
Solution Approach 1:
The patent combines multiple address lines into a single shared address bus, reducing the total number of signal toggles. Instead of multiple address lines toggling simultaneously to reach different block RAMs, a single address bus carries the address information that is then decoded, significantly reducing dynamic power consumption from address line toggling.
3Adaptability or versatility
If multiple address lines are routed to each block RAM in a group, then deeper address ports can be implemented, but critical timing delays increase
Solution Approach 1:
The patent segments the addressing function into two parts: a shared address bus that carries the address information and local decoding logic within each block RAM group. This segmentation allows the address to be transmitted once on the shared bus and then locally decoded, eliminating the need for long routed address lines and reducing critical timing delays while maintaining deep address port capability.
Data Source
AI summary
Systems and methods are disclosed for reducing or eliminating address lines that need to be routed to multiple related embedded memory blocks. In particular, one or more inputs are added to a block Random Access Memory (RAM) such that when one or more of the inputs are asserted, the address input to the Block RAM may be incremented prior to being used to retrieve data contents of the block RAM. Thus, if address <addr> is provided to the block RAM and the address increment signal is asserted, data may be read from location <addr+N> instead of <addr>, where N may be an integer. Block RAMs with such address arithmetic may be used to implement wide First-In-First-Out (FIFO) queues, wide memories, and/or data-burst accessible block RAMs.