Block Refreshing Semiconductor Memory Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current techniques for refreshing semiconductor memory devices are inefficient due to high power consumption, large space occupation by current sense amplifier circuitry, and prolonged refresh times, which can lead to data loss over time due to charge decay and charge pumping effects.
Innovation Solution
The method involves applying specific voltage potentials to memory cells to refresh data states in a single refresh cycle, using distinct voltage levels for binary 0 and binary 1 states, and employing a block refresh approach to maintain charge carriers in the electrically floating body region of memory transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current sense amplifier circuitry is used to read and write data states, then data states can be determined, but power consumption increases and space occupation increases
Solution Approach 1:
The patent extracts and eliminates the current sense amplifier circuitry from the memory refresh operation. Instead of using complex sense amplifiers to read and write data states, the invention applies voltage potentials directly to memory cells to refresh data states, removing the need for power-consuming sense amplifier circuitry while maintaining data state determination capability
Solution Approach 2:
The memory cells perform self-refresh by applying voltage potentials directly to themselves. The block refresh operation enables memory cells to maintain their own data states through direct voltage application, eliminating the need for external sense amplifier assistance and reducing overall power consumption
2Reliability
If current sense amplifier circuitry is used to read and write data states, then data states can be determined, but space occupation increases
Solution Approach 1:
The patent removes the current sense amplifier circuitry from the memory architecture. By using direct voltage potential application for block refresh operations, the invention eliminates the need for sense amplifier circuitry entirely, freeing up significant chip area for additional memory cells or other functions
Solution Approach 2:
The voltage potential application circuitry serves multiple functions: it performs block refresh operations, maintains data states, and enables data state determination without requiring separate sense amplifier circuitry. This multi-functionality reduces overall space occupation in the memory device
3Reliability
If sequential row addressing is used for refresh operations, then each row can be refreshed, but refresh time increases
Solution Approach 1:
The patent merges multiple row refresh operations into a single block refresh operation. By applying voltage potentials to entire blocks of memory cells simultaneously rather than addressing rows sequentially, the invention reduces the total refresh time from tens of milliseconds to a fraction of that time while maintaining data state integrity across all refreshed cells
Solution Approach 2:
The block refresh operation implements periodic refreshing of memory cell blocks at optimized intervals. This periodic block-level refreshing maintains data states more efficiently than continuous sequential row addressing, reducing the frequency and duration of refresh operations required
4Ease of operation
If negative gate bias is applied during read and write operations, then read/write operations can be performed, but charge carriers are reduced leading to data loss
Solution Approach 1:
The patent applies preliminary positive voltage potentials to memory cells before read and write operations to prevent charge carrier loss. By establishing a protective voltage state in advance, the invention counteracts the harmful charge pumping effect that would otherwise occur during operations with negative gate bias, maintaining charge carrier quantity and preventing data loss
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, minimizes data loss, and enables faster refresh operations, allowing for more efficient storage and retrieval of data states in semiconductor memory devices.
Implementation Method 1
a first gate coupled to a word line, wherein the first gate is spaced apart from, and capacitively coupled to, the first body region
Implementation Method 2
applying voltage potentials to the plurality of memory cells to refresh a plurality of data states stored in the plurality of memory cells
Data Source
AI summary
Techniques for block refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for block refreshing a semiconductor memory device. The method may comprise arranging a plurality of memory cells in one or more arrays of rows and columns. Each of the plurality of memory cells may comprise a first region coupled to a source line, a second region, a first body region disposed between the first region and the second region, wherein the body region may be electrically floating and charged to a first predetermined voltage potential, and a first gate coupled to a word line, wherein the first gate may be spaced apart from, and capacitively coupled to, the first body region. The method may also comprise applying voltage potentials to the plurality of memory cells to refresh a plurality of data states stored in the plurality of memory cells.