Block Selection Circuit for Semiconductor Memory
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Solution Overview
Problem
Conventional semiconductor devices face limitations in downsizing due to the large area occupied by high voltage generating circuits and pass transistor groups, which are necessary for selecting memory blocks, leading to increased device size.
Innovation Solution
A block selection circuit that includes a row decoder, a level shifter, and a selection signal generator to selectively output block selection voltages and couple local word lines to global word lines, reducing the need for multiple high voltage generating circuits and pass transistor groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage generating circuit and pass transistor group are provided for each memory block, then memory block selection is achieved, but the row decoder occupies a large area
Solution Approach 1:
The patent merges the high voltage generating circuits by providing a single shared high voltage generating circuit that serves all memory blocks, rather than having separate circuits for each block. This is achieved by using selection signals to control switching devices that route the block selection voltage to the appropriate pass transistor groups, thereby reducing the overall area of the row decoder while maintaining the capability to select any memory block.
2Reliability
If multiple high voltage generating circuits are used for each memory block, then block selection is reliable, but device size increases
Solution Approach 1:
The patent implements universality by designing a single high voltage generating circuit that can serve multiple memory blocks through the use of selection signals and switching devices. The block selection voltage generated by this single circuit is routed to different pass transistor groups based on the activation state of selection signals, allowing one circuit to perform the function of multiple circuits would otherwise be needed, thereby reducing device size.
Data Source
AI summary
A block selection circuit and a semiconductor device having the same may include a row decoder which includes a high voltage generating circuit configured to output a block selection voltage in response to upper addresses, switching circuits configured to receive the block selection voltage and a precharge high voltage, and forward the block selection voltage through one of the switching circuits that is selected in response to selection signals, and pass transistor groups configured to select a memory block in response to the forwarded block selection voltage.