Block Selection Circuit Layout for 3D Memory Wiring Bottlenecks
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently managing block selection circuits due to wiring bottlenecks and increased manufacturing complexity when additional shield lines are required to prevent interference between block selection signal lines.
Innovation Solution
The memory device incorporates a block selection circuit design where the block selection circuit regions are positioned on both sides of a central portion of the pass transistor region in a specific direction, avoiding placement on the second portion, thereby eliminating the need for additional shield lines and reducing wiring bottlenecks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If block selection circuit regions are positioned on both sides of the pass transistor region, then wiring bottlenecks are prevented and manufacturing complexity is reduced, but the layout optimization requires precise positioning to avoid interference between signal lines
Solution Approach 1:
The block selection circuit region is divided into multiple sub-regions (first block selection circuit region, second block selection circuit region, third block selection circuit region) positioned at different locations relative to the pass transistor region. This segmentation allows each region to be independently positioned and optimized, preventing wiring bottlenecks while maintaining manufacturing precision through modular design.
Solution Approach 2:
The patent utilizes multi-dimensional positioning by arranging block selection circuit regions not only on the left and right sides of the pass transistor region in the first direction but also extending into the second direction. This three-dimensional layout optimization prevents signal line interference while maintaining precise manufacturing through spatial distribution across multiple dimensions.
2Reliability
If additional shield lines are added to prevent interference between block selection signal lines, then signal interference is reduced, but manufacturing complexity and wiring bottlenecks increase
Solution Approach 1:
The patent extracts and repositions the block selection circuit regions away from the central pass transistor region, placing them on the periphery (first and second sides). This extraction eliminates the need for shield lines between signal lines, as the spatial separation itself provides interference protection, thereby reducing wiring complexity while maintaining reliability.
Solution Approach 2:
The pass transistor region acts as an intermediary spatial barrier that naturally separates block selection signal lines from each other. By positioning block selection circuit regions on opposite sides of this intermediary region, the patent achieves signal isolation without requiring additional shield lines, thus preventing interference while avoiding increased wiring complexity.
Data Source
AI summary
A memory device includes a first semiconductor layer including a slimming area, a first cell area and a second cell area arranged on both sides of the slimming area in a first direction, and a second semiconductor layer including a pass transistor region vertically overlapping with the slimming area, and a first block selection circuit region and a second block selection circuit region connected to the pass transistor region through a plurality of block selection signal lines, wherein the pass transistor region includes a first portion, a second portion and a third portion disposed on both sides of the first portion in a second direction perpendicular to the first direction, and wherein the first block selection circuit region and the second block selection circuit region are respectively disposed on both sides of the first portion of the pass transistor region in the first direction.