Block Stripe Allocation by Program-Erase Cycles for Memory Wear Leveling
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Solution Overview
Problem
Existing memory devices are discarded prematurely due to uneven wear and tear from program erase cycles, leading to inefficient utilization of block stripes and reduced lifespan.
Innovation Solution
A memory sub-system controller allocates block stripes based on program erase cycles, designating those with lower counts for cache memory and higher counts for flash translation layer memory, enabling flexible re-designation and shared garbage collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If block stripes are allocated uniformly without considering program erase cycles, then the memory sub-system structure is simple, but the memory device lifespan is reduced due to uneven wear
Solution Approach 1:
The system changes the allocation parameter from uniform distribution to program erase cycle-based distribution. By monitoring and comparing PEC counts across different block stripes, the system dynamically adjusts allocation decisions to balance wear across all block stripes, thereby extending memory device lifespan.
Solution Approach 2:
The system implements feedback by continuously monitoring program erase cycle counts for each block stripe and using this information to guide future allocation decisions. The controller compares PEC counts and redirects write operations to block stripes with lower PEC counts, creating a closed-loop wear-balancing system.
2Productivity
If block stripes with lower PEC counts are allocated for cache memory, then data storage efficiency is improved, but the management overhead increases
Solution Approach 1:
The system performs preliminary allocation by assigning block stripes with lower PEC counts to cache memory before they experience significant wear. This proactive approach ensures that high-performance block stripes are utilized for time-sensitive data operations while preventing premature degradation, thereby maintaining storage efficiency without requiring complex real-time management.
3Reliability
If block stripes are designated based on PEC counts, then wear leveling is achieved, but the flexibility for re-designation is reduced
Solution Approach 1:
The system implements dynamic re-designation capability where block stripe designations are not fixed but can be changed based on evolving PEC counts. The controller maintains the flexibility to re-allocate block stripes between cache memory and FTL functions as wear patterns change, allowing the system to adapt to varying operational conditions while maintaining wear leveling.
Data Source
AI summary
Various aspects of the present disclosure relate to a memory sub-system for allocating block stripes based on program erase cycles. A processing device may access a plurality of block stripes and may determine a program erase cycle count for each block stripe of the plurality of block stripes. The processing device may designate a first block stripe of the plurality of block stripes as a cache memory block stripe based on first block stripe having a lower program erase cycle count and may designate a second block stripe of the plurality of block stripes as an FTL block stripe based on the second block stripe having a higher program erase cycle count.