Block Tracking Entries for Cache Coherence Snoop Suppression

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

High-bandwidth memory-sharing devices, such as GPUs, generate excessive snoop traffic when using conventional cache coherence protocols, limiting their performance in general computing tasks due to the need for specialized memory management software.

Innovation Solution

Implementing a block tracking entry (BTE) table to suppress unnecessary snoop traffic by determining which cache lines are not in use, allowing memory-sharing devices to access shared memory without broadcasting snoop requests when indicated as 'no-line-snoop-required' in the BTE table.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional cache coherence protocols are used with high-bandwidth devices like GPUs, then cache coherence is maintained, but excessive snoop traffic is generated

Engineering Contradiction:
Improvecache coherenceVSAvoidsnoop traffic
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the cache coherence tracking at the block level rather than the cache line level. By introducing block tracking entries (BTEs) that track entire memory blocks, the system can suppress snoop traffic for blocks that are not in use while maintaining coherence for blocks that are actively accessed. This segmentation approach reduces the granularity of tracking, thereby reducing unnecessary snoop traffic while preserving cache coherence where needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by differentiating the treatment of different memory blocks. Instead of uniformly tracking all cache lines, the system tracks blocks at a coarser granularity and applies selective snoop suppression based on local usage patterns. Blocks that are determined to be in use maintain full coherence tracking, while blocks not in use have snoop traffic suppressed. This localized differentiation optimizes the balance between coherence and traffic reduction.

Inventive Principle:
Principle #3Local quality

2Productivity

If high-bandwidth devices are made non-coherent to reduce snoop traffic, then memory bandwidth is improved, but software complexity increases due to specialized memory management requirements

Engineering Contradiction:
Improvememory bandwidthVSAvoidsoftware complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements self-service by enabling memory-sharing devices to autonomously manage their own coherence state through block tracking entries. Each device maintains its own BTE table and can independently determine when snoop requests can be suppressed. This self-service capability allows high-bandwidth devices to operate with reduced snoop traffic while maintaining coherence, eliminating the need for specialized non-coherent memory software and reducing overall system complexity.

Inventive Principle:
Principle #25Self-service

3Object-generated harmful factors

If block tracking entries are used to suppress snoop traffic, then snoop traffic is reduced, but additional hardware structure is required

Engineering Contradiction:
Improvesnoop trafficVSAvoidhardware structure
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The patent applies universality by designing block tracking entries that serve multiple functions: tracking cache line usage status, determining snoop suppression eligibility, and maintaining coherence information. The BTE structure consolidates multiple tracking functions into a single data structure, reducing the need for separate hardware components. This multi-functional approach minimizes the additional hardware complexity while achieving snoop traffic reduction.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8856456B2Systems, methods, and devices for cache block coherence
Publication Date: 2014.10.07 APPLE INC
  • US8856456B2 patent drawing
  • US8856456B2 patent drawing
  • US8856456B2 patent drawing

AI summary

Systems, methods, and devices for efficient cache coherence between memory-sharing devices are provided. In particular, snoop traffic may be suppressed based at least partly on a table of block tracking entries (BTEs). Each BTE may indicate whether groups of one or more cache lines of a block of memory could potentially be in use by another memory-sharing device. By way of example, a memory-sharing device may employ a table of BTEs that each has several cache status entries. When a cache status entry indicates that none of a group of one or more cache lines could possibly be in use by another memory-sharing device, a snoop request for any cache lines of that group may be suppressed without jeopardizing cache coherence.