Blocked Convolution Computing for Variable Neural Network Dimensions

The patent divides the input feature map and weight data into multiple blocks along different dimensions (e.g., N, H, W, C dimensions). This segmentation allows the convolution operation to be processed in smaller, manageable units that can be efficiently mapped to hardware processing elements, thereby improving computing performance while maintaining support for various input dimensions through flexible block partitioning strategies.

The patent transforms the storage dimensions of input data and convolution kernels by changing parameter representations. Specifically, it reorganizes data layout from traditional NHWC or NCHW formats to block-based representations where data is partitioned into manageable units. This parameter transformation enables better utilization of hardware resources by aligning data access patterns with processor architecture, thus improving computing performance across different model configurations.

The patent automatically segments input data and kernels into blocks based on their dimensional characteristics. This segmentation is performed through systematic dimension transformation that divides large-dimensional inputs into smaller blocks suitable for hardware processing. The blocking operation simplifies the mapping between data and hardware resources while improving computing efficiency, as hardware can process fixed-size blocks more efficiently than variable-size data.

The patent introduces blocking dimensions by transforming the original data dimensions into blocked representations. By adding block-level organization to the data structure, it creates an additional dimension of organization that facilitates efficient hardware utilization. This dimensional transformation allows the system to maintain ease of operation through automated blocking while achieving improved computing efficiency through better hardware data alignment.

The patent implements segmentation through a systematic blocking mechanism that divides input data and kernels into standardized blocks. This segmentation approach improves computing efficiency by enabling efficient memory access patterns and parallel processing. The complexity introduced by blocking is managed through automated dimension transformation algorithms that systematically organize data without requiring complex manual intervention, thus balancing the trade-off between efficiency improvement and processing complexity.

The patent applies parameter changes by transforming data storage layouts from traditional formats to blocked representations. This transformation involves reorganizing data in memory according to block dimensions, which improves computing efficiency by aligning data access with hardware capabilities. The parameter transformation is performed through systematic dimension reordering and blocking operations that, while adding processing steps, follow consistent algorithms that minimize the increase in overall system complexity.