Self-Aligned Conductive Feature Layout for Parasitic Capacitance
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Solution Overview
Problem
The scaling down of semiconductor devices leads to challenges such as misalignment of conductive features, resulting in parasitic capacitance, breakdown pathways, and leakage current, which affect the yield and reliability of semiconductor devices.
Innovation Solution
A self-aligned scheme is employed to form conductive features with a blocking film that selectively deposits over the first conductive features, followed by dielectric layers that self-align to prevent misalignment, thereby reducing parasitic capacitance and ensuring proper contact between conductive features.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional alignment methods are used for conductive features, then manufacturing process is simpler, but misalignment occurs leading to parasitic capacitance and leakage current
Solution Approach 1:
The blocking film self-assembles on the conductive features through selective deposition, automatically defining the alignment boundaries without requiring external alignment marks or complex positioning systems. The film serves itself to create the precise alignment structure needed
Solution Approach 2:
The blocking film acts as an intermediary layer between the first and second conductive features, providing a physical and chemical barrier that ensures precise alignment while allowing the deposition process to proceed with standard manufacturing tolerances
2Manufacturing precision
If blocking film is selectively deposited to achieve self-alignment, then alignment precision improves, but manufacturing process complexity increases
Solution Approach 1:
The deposition process utilizes changes in surface energy and chemical affinity parameters to achieve selective film formation. By controlling these material parameters, the blocking film deposits only on desired surfaces without requiring complex masking or positioning procedures
3Reliability
If dielectric layers are deposited without self-alignment, then deposition process is simpler, but misalignment leads to parasitic capacitance
Solution Approach 1:
The dielectric layers self-align to the blocking film structure through conformal deposition, automatically following the topography created by the blocking film without requiring additional alignment steps or external guidance
Solution Approach 2:
The blocking film is deposited in advance to create the alignment template before the dielectric layers are formed. This preliminary structure guides subsequent deposition processes to ensure proper alignment and prevent parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The scheme enhances the yield and reliability of semiconductor devices by preventing or reducing parasitic capacitance and leakage current, allowing for improved manufacturing and functionality.
Implementation Method 1
depositing a blocking film over and physically contacting the first conductive feature
Implementation Method 2
depositing a first dielectric layer over and physically contacting the first inter-metal dielectric layer. The first dielectric layer may comprise a low-k dielectric material
Data Source
AI summary
In an embodiment, a method includes forming a first conductive feature in a first inter-metal dielectric (IMD) layer; depositing a blocking film over and physically contacting the first conductive feature; depositing a first dielectric layer over and physically contacting the first IMD layer; depositing a second dielectric layer over and physically contacting the first dielectric layer; removing the blocking film; depositing an etch stop layer over any physically contacting the first conductive feature and the second dielectric layer; forming a second IMD layer over the etch stop layer; etching an opening in the second IMD layer and the etch stop layer to expose the first conductive feature; and forming a second conductive feature in the opening.


