Blocking Patterns Stabilize Metal Contact Plugs in DRAM
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Solution Overview
Problem
As semiconductor devices integrate more densely, the increased height of capacitors in DRAMs leads to higher aspect ratios of metal contact plugs, reducing the overlap margin between these plugs and bit lines, causing misalignment and potential short circuits that deteriorate the operation characteristics of the device.
Innovation Solution
The formation of blocking patterns around bit lines in the core and peripheral regions of the semiconductor substrate, simultaneously with storage node contact plugs, helps stabilize contact between metal contact plugs and bit lines, even when misalignment occurs due to decreased overlap margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor height is increased to secure capacitance in high integration DRAM, then capacitance is sufficiently secured, but aspect ratio of metal contact plugs increases and overlap margin with bit lines decreases
Solution Approach 1:
The patent forms blocking patterns around bit lines before forming metal contact plugs. These blocking patterns are created in advance to define precise boundaries and guide the subsequent formation of contact plugs, ensuring accurate alignment even when overlap margins are reduced due to high integration requirements
Solution Approach 2:
The blocking patterns serve as intermediary structures between the bit lines and metal contact plugs. These patterns act as alignment references and physical barriers that prevent misalignment, mediating the relationship between the capacitor structures requiring high capacitance and the contact plugs requiring precise alignment
2Productivity
If overlap margin between metal contact plugs and bit lines is decreased due to high integration, then device density increases, but misalignment between contact plugs and bit lines occurs causing short circuits
Solution Approach 1:
Blocking patterns are formed in advance around bit lines to establish alignment boundaries before metal contact plug formation. This preliminary structuring ensures that even with reduced overlap margins for high density, the contact plugs can be accurately positioned without causing short circuits
Solution Approach 2:
The blocking patterns provide a protective buffer zone around bit lines that compensates for potential alignment variations. This beforehand cushioning prevents harmful short circuits by creating a controlled environment that accommodates manufacturing tolerances while maintaining high device density
Data Source
AI summary
A semiconductor device includes a semiconductor substrate divided into a cell array region, a core region, and a peripheral region. Bit lines are formed in the respective regions. Storage node contact plugs are formed in the cell array region, and blocking patterns are simultaneously formed around the bit lines of the core region and the peripheral region. Capacitors are formed in the cell array region to come into contact with the storage node contact plugs, and metal contact plugs are formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region. In the semiconductor device, even if the metal contact plugs are not aligned with the bit lines, the blocking pattern works to stabilize the contact between the metal contact plugs and the bit lines.