Bluetooth Receiver Interpolation Filtering Without Extra Oscillators
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Solution Overview
Problem
Bluetooth wireless receivers face challenges in achieving low power consumption and high sensitivity without requiring additional oscillators for generating whole multiple frequencies, which increases complexity and cost.
Innovation Solution
A receiver design that uses an interpolation filter to generate digitized samples at a lower sampling rate, allowing for a fractional multiple sampling frequency, and a counter to prevent processing of unusable samples, eliminating the need for a separate oscillator and maintaining effective ISI reduction with SRRC filters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sampling frequency is set to 6.5 MHz to match SRRC filters, then filter matching and ISI reduction are improved, but additional oscillator is required increasing chip area and power consumption
Solution Approach 1:
The patent changes the sampling frequency parameter from 6.5 MHz to 13 MHz, which is a whole multiple of the 1 MHz baseband signal rate. This parameter change eliminates the need for additional oscillators while maintaining effective filter matching through the interpolation filter that generates estimates of samples at the lower rate.
2Manufacturing precision
If sampling frequency is set to 6.5 MHz for SRRC filter matching, then ISI reduction is improved, but power consumption increases due to additional oscillator
Solution Approach 1:
The sampling frequency is changed from 6.5 MHz to 13 MHz, eliminating the need for additional oscillators and reducing power consumption. The interpolation filter compensates for the rate change to maintain ISI reduction performance.
Solution Approach 2:
An interpolation filter is introduced as an intermediary component that generates estimates of samples at the lower 6.5 MHz rate from the 13 MHz sampled signal. This mediator maintains the effective filter matching and ISI reduction without requiring the system to actually sample at 6.5 MHz.
3Area of stationary object
If sampling frequency is increased to 13 MHz to avoid additional oscillator, then chip area and power consumption are reduced, but demodulator complexity increases
Solution Approach 1:
The interpolation filter performs preliminary processing of the 13 MHz sampled signal to generate estimates of samples at the lower rate before the signal enters the demodulator. This preliminary action simplifies the demodulator's task by providing pre-processed data that maintains the benefits of lower-rate processing.
4Use of energy by stationary object
If sampling frequency is increased to 13 MHz to avoid additional oscillator, then power consumption is reduced, but demodulator complexity increases
Solution Approach 1:
The interpolation filter performs preliminary processing to generate rate-matched sample estimates before demodulation, reducing the power consumption associated with additional oscillators while managing demodulator complexity through pre-processed input data.
Data Source
AI summary
A receiver having circuitry for generating first digitized samples from a received analog signal at a first sampling rate, e.g. an ADC. An interpolating filter is used to generate second digitized samples which are estimates of samples obtainable by sampling the received analog signal at a second sample rate lower than the first sampling rate, second digitized samples being output at the first sampling rate and including at least one unusable sample. A circuit is provided for generating a signal for controlling components of the receive path downstream of the interpolation filter to prevent processing of the unusable second digitized samples.