BMC Clock Accuracy via FPGA RTC Monotonic Data
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Solution Overview
Problem
The baseboard management controller (BMC) in information handling systems faces challenges in maintaining accurate real-time clock information, especially after power interruptions or reboots, where the clock information may be reset to a build time or become inaccurate, leading to incorrect timestamping of system events.
Innovation Solution
The method involves initializing the BMC with clock information from a field programmable gate array (FPGA) RTC, which includes non-volatile hold registers to store clock data during power disruptions, and updating it with host RTC information to ensure monotonic and accurate timekeeping, preventing clock drift.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BMC uses a real-time clock that is initialized at boot, then the clock information is simple to implement, but the clock becomes inaccurate after power interruptions or reboots
Solution Approach 1:
The system performs preliminary action by capturing and storing monotonic clock information from the FPGA in non-volatile memory before power interruption occurs. This pre-captured time data is then restored after reboot, eliminating the need for complex continuous synchronization while maintaining accuracy.
Solution Approach 2:
The patent introduces an intermediary mechanism - a data structure containing monotonic clock information captured from the FPGA - that mediates between the FPGA's accurate time source and the BMC's real-time clock. This intermediary preserves time accuracy without requiring direct complex integration between components.
2Measurement precision
If the BMC resets the real-time clock to build time after initialization, then the system is easy to restart, but event timestamping becomes incorrect
Solution Approach 1:
The system performs preliminary action by capturing and storing monotonic clock information from the FPGA in non-volatile memory before power interruption occurs. This pre-captured time data is then restored after reboot, eliminating the need for complex continuous synchronization while maintaining accuracy.
Solution Approach 2:
The patent uses copying by creating a data structure that copies the essential monotonic clock information from the FPGA's time source. This copied time data is stored in the BMC's non-volatile memory and restored after reboots, providing accurate timestamps without complex system integration.
3Reliability
If the system uses multiple clock sources (FPGA RTC and host RTC), then clock accuracy is improved, but the time keeping mechanism becomes more complex
Solution Approach 1:
The system applies taking out by extracting only the essential monotonic clock information from the FPGA's time source into a simplified data structure. This extracted time data is stored in non-volatile memory and restored after reboots, eliminating the need for complex continuous synchronization between multiple clock sources while maintaining accuracy.
Data Source
AI summary
A method may include initializing operation of a baseboard management controller at an information handling system. The baseboard management controller includes a real time clock. The method further includes receiving clock information from a real time clock circuit included at a field programmable gate array. The clock information at the real time clock at the baseboard management controller can be updated with the clock information received from the real time clock circuit included at the field programmable gate array.