BMC Reset via Hardware Watchdog and CPLD

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Solution Overview

Problem

In server architecture, a malfunctioning or hung baseboard management controller (BMC) severely impacts the performance and capability of server systems, as existing technologies lack effective mechanisms for timely and reliable reset or recovery.

Innovation Solution

The implementation of a hardware watch-dog-timer (HW WDT) circuit and complex programmable logic device (CPLD) to monitor heartbeat signals and health conditions of the BMC, with the CPLD generating reset signals to address component failures, and a physical layer IC for remote management and communication, enabling remote reset capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a BMC is used to monitor and control server system management functions, then system management capability is improved, but the risk of system failure increases when the BMC malfunctions or hangs

Engineering Contradiction:
Improvesystem management capabilityVSAvoidsystem reliability when BMC fails
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent introduces a CPLD (Complex Programmable Logic Device) as an intermediary component between the BMC and the system components. The CPLD independently monitors the BMC's health status through heartbeat signals and can directly reset the BMC or other system components without requiring BMC intervention. This mediator architecture ensures that even when the BMC fails, the CPLD can maintain system control and perform recovery operations, thus resolving the reliability issue while preserving management capabilities.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If existing BMC reset mechanisms are used, then reset functionality is provided, but the reset process is delayed and unreliable when BMC hangs

Engineering Contradiction:
Improvereset functionalityVSAvoidreset delay time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent implements a hardware watchdog timer (HW WDT) circuit that continuously monitors BMC heartbeat signals in advance. When the BMC fails to send heartbeat signals within a predetermined time threshold, the HW WDT automatically triggers a reset signal through the CPLD. This preliminary monitoring and automatic trigger mechanism eliminates the need for manual intervention and reduces reset delay time, ensuring timely recovery when the BMC hangs.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If BMC health monitoring is implemented, then system health awareness is improved, but the complexity of the monitoring system increases

Engineering Contradiction:
ImproveBMC health monitoring accuracyVSAvoidmonitoring system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a self-service monitoring architecture where the CPLD autonomously monitors BMC health status by receiving and evaluating heartbeat signals from the BMC. The CPLD contains internal logic that automatically compares heartbeat intervals against predetermined thresholds and triggers appropriate actions without external intervention. This self-service approach provides precise health monitoring while minimizing system complexity by consolidating monitoring and control functions within the CPLD itself, eliminating the need for separate complex monitoring systems.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10846160B2System and method for remote system recovery
Publication Date: 2020.11.24 QUANTA COMPUTER INC
  • US10846160B2 patent drawing
  • US10846160B2 patent drawing
  • US10846160B2 patent drawing

AI summary

The present disclosure provides a system and method for resetting a hang-up baseboard management controller (BMC), or another component of a server system using a hardware watch-dog-timer (HW WDT) circuit and/or complex programmable logic device (CPLD). The HW WDT circuit can monitor heartbeat signals from the BMC, and determine the health condition of the BMC. In an event that the BMC's health condition fails to meet a predefined criterion, the HW WDT circuit generates a reset signal to reset the BMC. The CPLD can collect from the BMC, health information of components of the server system. The CPLD can also collect the BMC's health condition from the HW WDT circuit. Upon determining which specific component of the server system hangs up, the CPLD can generate a reset signal to reset the specific component.