BNNT Low-k Spacer Structure for Interconnect RC Delay Reduction

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Solution Overview

Problem

Current transistor structures face challenges with RC delay due to high dielectric constants in interconnects, particularly with existing low-k materials like SiCOH, which compromise structural stability and are prone to ionic diffusion, limiting faster transistor performance.

Innovation Solution

Incorporating boron nitride nanotubes (BNNTs) as spacer layers in field-effect transistors to reduce the dielectric constant, utilizing single-walled or multi-walled BNNTs with specific orientations and radii to achieve a dielectric constant below 2, thereby minimizing RC delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If porous low-k materials like SiCOH are used to reduce dielectric constant, then RC delay is reduced, but structural stability deteriorates and ionic diffusion increases

Engineering Contradiction:
ImproveRC delayVSAvoidstructural stability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The patent employs boron nitride nanotubes (BNNTs) as a composite material alternative to porous SiCOH. BNNTs provide both low dielectric constant (k<2) and high structural stability with resistance to ionic diffusion, combining the benefits of low-k performance with mechanical reliability that porous materials lack.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the material parameter from porous SiCOH (k=2.4) to BNNTs (k<2), achieving a lower dielectric constant while simultaneously improving structural stability. This parameter change resolves the contradiction by finding a material that satisfies both low-k requirements and structural integrity.

Inventive Principle:
Principle #35Parameter changes

2Speed

If transistor size is decreased to increase operation speed, then transistor speed increases, but interconnect RC delay increases

Engineering Contradiction:
Improvetransistor operation speedVSAvoidinterconnect RC delay
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent changes the dielectric material parameter in interconnects from conventional materials to BNNTs with k<2. This parameter change reduces the capacitive component of RC delay, allowing smaller transistor dimensions to be used without proportionally increasing interconnect delay, thus maintaining the speed advantage.

Inventive Principle:
Principle #35Parameter changes

3Speed

If dielectric constant is reduced below 2.4 to improve transistor speed, then transistor speed increases, but material availability and structural stability worsen

Engineering Contradiction:
Improvetransistor speedVSAvoidmaterial availability
Core Design Contradiction:
SpeedVSAdaptability or versatility

Solution Approach 1:

The patent introduces BNNTs as a novel composite material that achieves dielectric constant k<2, overcoming the limitation of available materials. BNNTs provide both the required low-k property for speed improvement and sufficient structural stability, expanding the available material options for low-k applications.

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

BNNTs provide a stable and effective solution to reduce RC delay, offering a dielectric constant as low as 1.6, enhancing transistor speed and stability while maintaining structural integrity.

Implementation Method 1

Incorporating boron nitride nanotubes (BNNTs) as spacer layers in field-effect transistors to reduce the dielectric constant, utilizing single-walled or multi-walled BNNTs with specific orientations and radii to achieve a dielectric constant below 2, thereby minimizing RC delay

Methodology Applied
Scientific EffectDielectric constant reduction: Dielectric Permittivity

Data Source

PatentUS20260015234A1Boron-nitride nanotubes (BNNT) for low-k dielectrics spacers and faster interconnects
Publication Date: 2026.01.15 SAMSUNG ELECTRONICS CO LTD
  • US20260015234A1 patent drawing
  • US20260015234A1 patent drawing
  • US20260015234A1 patent drawing

AI summary

A structure includes boron nitride nanotubes, wherein the structure (i) is an extension region in a field-effect transistor or (ii) comprises a metallic interconnect to reduce the dielectric constant and therefore the RC-delay in the device. Also, a field-effect transistor structure includes a low-k spacer layer between metallic interconnects, wherein the low-k spacer layer includes boron nitride nanotubes. In addition, a method for reducing RC delay in an integrated circuit includes forming a component of the integrated circuit from boron nitride nanotubes.