Workload-Adaptive Board Cache Layout for Storage Arrays

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Solution Overview

Problem

Existing storage arrays face inefficiencies in managing cache resources due to static allocation strategies that do not adapt to varying input/output workloads, leading to suboptimal performance and resource utilization.

Innovation Solution

Implementing a dynamic cache layout distribution system that adjusts cache slot allocations based on input/output workload characteristics, utilizing a system-level and board-level cache layout distribution model to optimize memory usage and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If static cache allocation strategy is used, then device complexity is reduced and ease of operation is improved, but cache resource utilization deteriorates and storage array performance deteriorates

Engineering Contradiction:
Improvecache management simplicityVSAvoidstorage array performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements dynamic cache allocation that automatically adjusts cache slot distribution across multiple boards based on real-time workload characteristics. The system monitors IO patterns, queue depths, and board performance metrics, then dynamically reallocates cache resources to high-performing boards during peak workloads and redistributes during low-utilization periods, transforming static cache management into an adaptive system that optimizes performance without manual intervention

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system establishes a feedback loop where cache allocation decisions are continuously refined based on performance monitoring. The controller tracks cache hit/miss ratios, IO completion rates, and board utilization metrics, using this feedback to adjust cache slot allocations in subsequent time periods. This closed-loop control enables the system to learn from past performance and automatically optimize cache distribution patterns

Inventive Principle:
Principle #23Feedback

2Device complexity

If static cache allocation strategy is used, then device complexity is reduced, but cache resource utilization deteriorates

Engineering Contradiction:
Improvecache management system complexityVSAvoidcache resource utilization
Core Design Contradiction:
Device complexityVSQuantity of substance

Solution Approach 1:

The patent implements dynamic cache allocation that automatically adjusts cache slot distribution across multiple boards based on real-time workload characteristics. The system monitors IO patterns, queue depths, and board performance metrics, then dynamically reallocates cache resources to high-performing boards during peak workloads and redistributes during low-utilization periods, transforming static cache management into an adaptive system that optimizes performance without manual intervention

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the allocation parameters of cache slots based on workload conditions. When workload intensity increases, the system increases cache slot allocation to boards handling high-volume IO operations. When workload decreases, it reduces allocation to maintain optimal utilization. This dynamic parameter adjustment enables efficient cache resource usage while maintaining system simplicity through automated control

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12430248B2Board level dynamic cache layout distribution
Publication Date: 2025.09.30 DELL PROD LP
  • US12430248B2 patent drawing
  • US12430248B2 patent drawing
  • US12430248B2 patent drawing

AI summary

One or more aspects of the present disclosure relate to cache layout optimization. In embodiments, an input/output (IO) workload is received by a storage array. Additionally, a system-level cache layout distribution model is established based on one or more characteristics of the IO workload. Further, cache slot allocations are dynamically adjusted for each cache segment of global memory for each board based on the system-level cache layout distribution model and the one or more characteristics of the IO workload.