Body-Biased Frequency Divider for Low-Voltage High-Speed CMOS
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional frequency dividers in wireless communication systems face challenges in maintaining high-speed operation at low voltage levels, particularly in deep submicron CMOS processes where power supply voltage is reduced, making it difficult to support MOS transistors in the saturation region.
Innovation Solution
A frequency divider design that incorporates a body bias voltage generator to control PMOS and NMOS body bias voltages, which are proportional to the input signal frequency, allowing the operation points of flip-flops to be adjusted, thereby enabling high-speed operation even at low voltages. This design uses TSPC flip-flops and includes a body bias voltage generator with input signal detectors and charge pumps to adjust the voltage levels of PMOS and NMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If power supply voltage is lowered to about 1V in deep submicron process, then power consumption is reduced, but it becomes difficult to supply sufficient power supply voltage for biasing MOS transistors in saturation region
Solution Approach 1:
The patent changes the biasing parameters by introducing separate body bias voltages (VBn for NMOS, VBp for PMOS) that are dynamically adjusted based on the input signal frequency. This allows the transistors to maintain saturation operation even when the supply voltage is lowered to 1V, resolving the contradiction between low power consumption and reliable transistor operation.
2Reliability
If body bias voltage is increased to maintain transistor saturation, then operation reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic body bias voltage adjustment where VBn and VBp are varied in real-time according to the input signal frequency. At lower frequencies, lower bias voltages are sufficient, reducing power consumption. At higher frequencies, increased bias voltages ensure saturation operation. This dynamic adaptation resolves the contradiction between reliability and power consumption.
3Speed
If conventional CML configuration is used, then high-speed operation is achieved, but it cannot operate at high speed at low voltage
Solution Approach 1:
The patent modifies the conventional CML configuration by introducing dynamically controllable body bias voltages that are adjusted based on input frequency. This parameter change enables the circuit to maintain high-speed operation characteristics across a wide voltage range, including low voltage conditions where conventional CML would fail to operate reliably.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively controls the operation speed and power consumption of the frequency divider by adjusting the body bias voltages, allowing for efficient high-speed operation at low voltages, as demonstrated by the increase in maximum operating frequency and current consumption with varying body bias voltage levels.
Implementation Method 1
a body bias voltage generator for generating a body bias voltage including a PMOS body bias voltage and an NMOS body bias voltage whose voltage levels are controlled according to an input signal
Data Source
AI summary
A frequency divider for a wireless communication system is provided. A frequency divider includes a body bias voltage generator and a divider. The body bias voltage generator generates a body bias voltage including a PMOS body bias voltage and an NMOS body bias voltage whose voltage levels are controlled according to an input signal. The divider includes a plurality of flip-flops whose operation points are determined according to the body bias voltage, and generates an output signal by dividing a frequency of the input signal by N. Each of the flip-flops may include a PMOS logic and an NMOS logic. The PMOS logic may include a plurality of PMOS transistors whose operation points are determined according to the PMOS body bias voltage. The NMOS logic may be connected electrically to the PMOS logic and include a plurality of NMOS transistors whose operation points are determined according to the NMOS body bias voltage.