Body-Tied Fin Flash Memory Coupling Ratio Optimization
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Solution Overview
Problem
Existing flash memory cell structures face challenges with increasing leakage current and reduced punch-through voltage due to channel shortening, leading to low programming speed and increased disturbance between adjacent cells, particularly with the use of high dielectric constant materials like HfO2, which exacerbate coupling ratios and drain disturbances.
Innovation Solution
A body-tied fin structure flash memory cell design featuring a dispersed floating gate structure with stacked layers on the sidewalls and top surface of fin structures, where adjacent fins share a dispersed structure, and a control gate is formed with a polysilicon layer, optimizing the coupling ratio between the control gate and floating gate while reducing noise from adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If HfO2 material with high dielectric constant is used to improve coupling ratio, then programming speed is improved, but physical thickness increases causing severe disturbance between adjacent cells
Solution Approach 1:
The floating gate is segmented into multiple discrete stacked layers instead of a continuous structure. This segmentation allows the electric field to be distributed across multiple interfaces, enhancing the coupling ratio between control gate and floating gate while reducing the overall disturbance to adjacent cells through spatial distribution of the charge storage function
Solution Approach 2:
The patent employs a composite structure combining HfO2 material with stacked layer configuration. The HfO2 provides high dielectric constant for strong coupling, while the stacked layer arrangement with air gaps or different dielectric materials creates a composite structure that optimizes both coupling ratio and reduces cross-cell disturbance
2Speed
If large-area overlap between drain and gate is increased to improve coupling ratio, then programming speed improves, but drain disturbance increases
Solution Approach 1:
The floating gate structure extends into the vertical dimension with multiple stacked layers on the sidewalls and top surface of the fin. This three-dimensional configuration increases the effective overlap area between drain and floating gate without requiring larger planar dimensions, thereby improving coupling ratio while maintaining compact cell footprint and reducing drain disturbance
3Quantity of substance
If channel length is shortened to increase density, then memory capacity improves, but leakage current increases and punch-through voltage decreases
Solution Approach 1:
The body-tied fin structure segments the channel into multiple regions along the fin length, with different doping concentrations applied to different segments. This allows optimization of each segment's electrical characteristics, maintaining high punch-through voltage and low leakage current even with shortened overall channel length, thereby enabling higher density while preserving reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances the coupling ratio between the control gate and floating gate, reduces cross-talk between cells, and improves programming speed, addressing issues of leakage current and voltage requirements, thereby supporting the shrinking of flash memory structures with high industrial utilization value.
Implementation Method 1
the dispersed structure is configured to be at a predetermined location along the elongated shape, wherein the dispersed structure is disposed on a top surface and two opposing sidewalls of each of the plurality of fin structures
Implementation Method 2
enhances the coupling ratio between the control gate and floating gate
Data Source
AI summary
The present disclosure provides a device structure for increasing the coupling ratio of a body-tied fin flash memory cell. The device includes a plurality of elongate fin structures arranged in parallel in an active layer on a substrate, a floating gate disposed on the top surface and the opposing sidewalls of each of the fin structures and at a predetermined location on the elongated fin, and dispersed structure. The dispersed structure comprises a plurality of stacked layers parallel to the substrate, spaced evenly apart; and two adjacent fin structures share one dispersed structure at their sidewalls. This device increases the distance between adjacent floating gates, reduces coupling capacitance, and reduces the disturbance between the cells, which is conducive to increasing the drain voltage, improving the programming speed, and further reducing the gate voltage. More optimization options for subsequent shrinking of the flash memory cells can be provided.