Bump-on-Lead Flip Chip Interconnect for Parasitic Reduction
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Solution Overview
Problem
Conventional flip chip interconnection technologies are limited by high costs due to the need for multiple layer substrates, which introduce electrical parasitics and reduce package performance, and are hindered by the inefficiencies of conventional capture pad-based interconnects.
Innovation Solution
The implementation of 'Bump-on-Lead' (BoL) or 'Bump-on-Narrow Pad' (BoNP) interconnects, which allow for more efficient routing in a single metal layer, reducing substrate complexity and eliminating vias and stubs, while providing a microstrip controlled impedance for signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional capture pad-based interconnects are used, then interconnection reliability is maintained, but substrate complexity increases and cost increases due to multiple layer requirements
Solution Approach 1:
The invention extracts the interconnection function from the conventional capture pad structure and relocates it to the lead structure. By forming bump joints directly on the leads rather than on separate capture pads, the patent eliminates the need for complex multi-layer substrate routing while maintaining reliable electrical connection. This extraction of the interconnection function to a simpler location resolves the contradiction between substrate complexity and reliability.
Solution Approach 2:
The invention transitions from a planar capture pad layout to a three-dimensional lead structure for interconnection. By utilizing the vertical dimension of the leads and forming bumps that extend upward from the lead surfaces, the patent achieves reliable interconnection without requiring multiple horizontal substrate layers, thereby reducing substrate complexity while maintaining connection integrity.
2Reliability
If multiple layer substrates are used for routing, then interconnection functionality is achieved, but electrical parasitics increase and performance decreases
Solution Approach 1:
The invention extracts the signal routing function from the multi-layer substrate and consolidates it into single-layer lead traces. By forming bump joints directly on the leads, the patent eliminates the need for vertical vias and multiple routing layers, thereby removing the sources of electrical parasitics such as via inductance and inter-layer capacitance while maintaining complete interconnection functionality.
Solution Approach 2:
Instead of routing signals through multiple substrate layers from capture pads to external pins, the invention inverts the approach by bringing the interconnection point down to the lead level. This inversion eliminates the need for upward routing through multiple layers and reduces the signal path through parasitic-filled substrate material, improving package performance.
3Ease of manufacture
If conventional fan out routing is used, then interconnection coverage is achieved, but manufacturing cost increases due to multiple metal layers
Solution Approach 1:
The invention extracts the interconnection function from the complex multi-layer metal routing system and relocates it to the lead structure. By forming bumps directly on the leads, the patent eliminates the need for multiple patterned metal layers and their associated photolithography and etching steps, significantly reducing manufacturing cost and process complexity.
Solution Approach 2:
The invention discards the conventional capture pad and multi-layer routing structure, recovering only the essential function of electrical interconnection through the simplified lead-based bump joint approach. This discarding of unnecessary structural complexity directly reduces manufacturing cost while maintaining interconnection coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces the overall cost of flip chip packages, improves performance by eliminating electrical parasitics, and maintains reliability, with tapered interconnect structures and composite materials optimizing contact areas to manage thermal expansion mismatches.
Implementation Method 1
solder joint flip chip interconnection
Implementation Method 2
manage thermal expansion mismatches
Data Source
AI summary
A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.