Bond-on-Pad Circuit Packaging to Eliminate SoP Bump Processing

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Solution Overview

Problem

Current solder-on-pad (SoP) technology in chip packages is costly, time-consuming, and prone to yield losses due to missing bumps and dimensional tolerance issues.

Innovation Solution

The implementation of bond-on-pad (BoP) substrate technology, which eliminates the need for solder bumps on bump pads, reducing process complexity and costs, and improving manufacturing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If solder-on-pad (SoP) technology is used for chip packages, then reliable electrical connections can be achieved, but manufacturing costs increase, cycle time extends, and yield losses occur due to missing bumps and dimensional tolerance issues

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidmanufacturing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the solder bump formation step from the traditional SoP process. Instead of forming solder bumps on substrate pads and then attaching chips, the invention directly attaches chip bumps to substrate pads without intermediate solder bumps, eliminating the complex solder paste printing, reflow, and inspection steps while maintaining reliable electrical connections

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent inverts the traditional bonding sequence. Instead of substrate pad → solder bump → chip bump (SoP), the invention uses substrate pad → chip bump direct attachment (BoP). This inversion eliminates the need for solder bump formation and reduces the process to essential steps only, improving productivity without sacrificing connection reliability

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If solder-on-pad (SoP) technology is used for chip packages, then electrical connections can be established, but process complexity and material costs increase

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the solder bump formation sub-process from the traditional SoP methodology. By extracting the solder paste printing, reflow soldering, and bump inspection steps, the invention simplifies the overall process flow to direct bump attachment, reducing both process complexity and material costs while preserving electrical connection reliability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent eliminates expensive solder materials and associated consumables (solder paste, flux, stencils) by using direct bump attachment. The chip bumps themselves serve as the bonding element without requiring additional solder, reducing material costs and process complexity while maintaining reliable electrical connections

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Reliability

If solder-on-pad (SoP) technology is used for chip packages, then joints can be formed, but manufacturing cycle time increases due to multiple process steps

Engineering Contradiction:
Improvejoint formation reliabilityVSAvoidmanufacturing cycle time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent enables continuous bump attachment by eliminating the discrete solder bump formation steps. The direct BoP process allows uninterrupted attachment of chip bumps to substrate pads, removing waiting times for solder reflow and inspection, thereby reducing manufacturing cycle time while maintaining joint formation reliability

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent skips the intermediate solder bump formation and inspection steps that traditionally slow down manufacturing. By rushing directly from substrate preparation to chip bump attachment, the invention eliminates time-consuming intermediate processes while ensuring reliable joint formation through precise direct bonding

Inventive Principle:
Principle #21Skipping (Rushing through)

Data Source

PatentUS12322690B2Circuit packages and fabrication methods using bond-on-pad (BoP) substrate technology
Publication Date: 2025.06.03 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US12322690B2 patent drawing
  • US12322690B2 patent drawing
  • US12322690B2 patent drawing

AI summary

One or more implementations of the subject technology may enable a bond-on-pad (BoP) substrate technology that can eliminate the need to utilize a solder-on-pad (SoP) process. Unlike an SoP process, a BoP Process does not require a solder bump to be formed on a bump pad to attach a joint to a bump pad. The size of an opening on a bump pad for a BoP process may be larger than that of an SoP process. A BoP process may use a solder mask having multiple thicknesses and may be thinner near the bump pads. A BoP process may use a joint having a copper pillar and a solder cap. A BoP process can be used with an underfill or a molding compound technology.