Bond Pad Overcoat Layout for High-Voltage Arcing Suppression

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Solution Overview

Problem

High voltage wafer probe testing of semiconductor dies can result in arcing between bond pads and nearby ground traces, leading to device damage and reduced yield due to dielectric breakdown of air, especially for high power semiconductor devices like power FETs.

Innovation Solution

The implementation of bond pads with a protective overcoat having a dielectric constant less than 3.8, and the use of floating conductive traces or iterative design of bond pad shapes to reduce electric field strength, including the use of materials with low dielectric constants and non-linear field grading films to smooth electric fields and prevent arcing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high voltage is applied to bond pads during wafer probe testing, then device functionality can be verified, but arcing occurs between bond pads and ground traces causing device damage

Engineering Contradiction:
Improvedevice functionality verificationVSAvoidarcing damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A protective overcoat layer is introduced as an intermediary between the bond pad and the surrounding environment. This overcoat has a dielectric constant less than 3.8 (lower than conventional materials like silicon dioxide with k=3.9), which reduces the electric field strength at the bond pad edge and prevents arcing to nearby ground traces during high voltage testing

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The dielectric constant parameter of the protective overcoat material is changed from conventional values (k≥3.9) to lower values (k<3.8). This parameter change directly reduces the electric field concentration at bond pad edges, preventing dielectric breakdown of air and arcing events during high voltage operation

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If conventional protective overcoat materials with high dielectric constants are used, then bond pads are protected from environmental damage, but electric field concentration increases causing arcing

Engineering Contradiction:
Improveenvironmental protectionVSAvoidelectric field concentration
Core Design Contradiction:
Object-affected harmful factorsVSObject-generated harmful factors

Solution Approach 1:

The dielectric constant parameter of the protective overcoat is reduced from conventional values (k≥3.9) to lower values (k<3.8). This parameter change simultaneously maintains environmental protection functionality while reducing electric field concentration at bond pad edges, preventing arcing events

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The protective overcoat is formed using composite material structures including low-k dielectric layers, porous dielectric materials, or combinations of different dielectric layers. These composite structures provide both environmental protection and reduced electric field concentration through their unique dielectric properties

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces arcing events during wafer probe testing and device use, enhancing the reliability and yield of semiconductor devices by minimizing electric field hotspots and device failures.

Implementation Method 1

the protective overcoat having a dielectric constant of less than 3.8

Methodology Applied
Scientific EffectDielectric constant: Dielectric Permittivity

Implementation Method 2

arcing occurs when the electric field between the points exceeds the dielectric breakdown of air

Methodology Applied
Scientific EffectElectric field: Electric Field

Data Source

PatentUS11881461B2Electric field control for bond pads in semiconductor device package
Publication Date: 2024.01.23 TEXAS INSTRUMENTS INC
  • US11881461B2 patent drawing
  • US11881461B2 patent drawing
  • US11881461B2 patent drawing

AI summary

In a described example, an apparatus includes: a semiconductor die having bond pads on a device side surface, the semiconductor die having a ground plane spaced from the bond pads by a spacing distance. The bond pads have an upper surface for receiving a ball bond, and an outer boundary, the bond pads having vertical sides extending from the upper surface to a bottom surface, the bottom surface formed over the device side surface of the semiconductor die. A protective overcoat (PO) is formed overlying the ground plane and overlying the vertical sides of the bond pads, and overlying a portion of the upper surface of the bond pads, and having an opening exposing the remaining portion of the upper surface of the bond pads, the protective overcoat having a dielectric constant of less than 3.8.